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<!--Data Space General Purpose Registers ( 00 - 1F ) Data   Space I / O Registers ( 20 - 5F ) { 00 - 3F } SRAM ( 60-DF ) EEAR EEDR EECR UDR USR UCR UBRR ACSR TCCR0 TCNT0 TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL ICR1H ICR1L WDTCR SREG SPL GIMSK GIFR TIMSK TIFR MCUCR PORTB DDRB PINB PORTD DDRD PIND 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF R0  R1  R2  R3  R4  R5  R6  R7  R8  R9  R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 The memory spaces in  the AVR architecture are all  linear and regular memory maps. The 128 bytes data SRAM ,  Register File and I/O Registers  can be easily accessed through the five different  addressing modes supported in  the AVR architecture. ( LD Data , ST Data ) { IN Port, OUT Port } Accessing by different Data Transfer Instructions --><OBJECT classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000"
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