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<!--SPI  for  ISP 8 Bit Shift Register SPI Clock Generator AT90S2313 MISO MOSI SCK SPI Serial Interface for In-System Programming RESET GND   Both the program and data memory arrays can be programmed using the serial SPI bus while RESET is  pulled to GND.  The serial interface consists of  pins SCK, MOSI and MISO .   The program and EEPROM  memory arrays have separate  address spaces: $0000 to $03FF for  program Flash memory and $000 to  $07F for EEPROM data memory.   Either an external clock is supplied  at pin XTAL1 or a crystal needs to  be connected across pins XTAL1  and XTAL2.    The minimum low  and high periods  for the serial clock (SCK) input are  defined as follows: Low: > 2 XTAL1 clock cycle High: > 2 XTAL1 clock cycles Refer to device data sheet for  Serial Programming Algorithm --><OBJECT classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000"
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