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<!--Interrupt  Unit The I-bit is cleared  by hardware  after an interrupt has occurred, and is set  by the RETI instruction  to enable subsequent interrupts. Hardware Pin,Power-on,Watchdog External Interrupt Request 0 External Interrupt Request 1 CAPT1 Timer/Counter1 Capture Event COMP1 Timer/Counter1 Compare Match OVF1 Timer/Counter1 Overflow OVF0 Timer/Counter0 Overflow UART, RX Complete UART Data Register Empty UART, TX Complete Analog Comparator 1 2 3 4 5 6 7 8 9 10 11 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A RESET INT0 INT1 TIMER1 CAPT1 TIMER1 COMP1 TIMER1 OVF1 TIMER0 OVF0 UART  RX UART  UDRE UART  TX ANA_COMP Interrupt Definition Vector Address Source Reset and Interrupt Vectors The MCU provides 10 different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space. All the interrupts are assigned individual enable bits that must be set (one)  together with the I-bit in the Status Register in order to enable the interrupt.  The complete list of vectors is shown in the table.  The table determines the priority levels of the different interrupts.  The lower the address, the higher the priority level.  RESET has the highest priority, and next is INT0. The instructions placed in addresses $0000-$000A must be an RJMP  instruction to the appropriate handling routine.  If the program never enables an interrupt source, the Interrupt Vectors are not used,  and regular program code can be placed at these locations.  --><OBJECT classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000"
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