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<!--T/C1 Clock Sourse When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. T/C1 CONTROL REGISTER (TCCR1B) CS12 CS11 CS10 TCK1 CK '0' CK / 64 CK / 8 CK / 1024 CK / 256 T1 Stop, the Timer/Counter1 is stopped. External Pin T1, rising edge External Pin T1, falling edge Timer/Counter1 - Clock Sourse --><OBJECT classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000"
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