📄 cnt4_din.rpt
字号:
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda_exercise\cnt4_din\cnt4_din.rpt
cnt4_din
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 03 OR2 2 2 0 2 |LPM_ADD_SUB:34|addcore:adder|pcarry1
- 3 - B 03 OR2 1 2 0 1 |LPM_ADD_SUB:34|addcore:adder|pcarry2
- 4 - B 03 DFFE + 1 1 1 0 q13 (:10)
- 6 - B 03 DFFE + 1 1 1 1 q12 (:11)
- 2 - B 03 DFFE + 2 1 1 1 q11 (:12)
- 8 - B 03 DFFE + 1 0 1 2 q10 (:13)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\eda_exercise\cnt4_din\cnt4_din.rpt
cnt4_din
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda_exercise\cnt4_din\cnt4_din.rpt
cnt4_din
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: f:\eda_exercise\cnt4_din\cnt4_din.rpt
cnt4_din
** EQUATIONS **
clk : INPUT;
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = q10;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = q11;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = q12;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = q13;
-- Node name is ':13' = 'q10'
-- Equation name is 'q10', location is LC8_B3, type is buried.
q10 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !din0 & q10
# din0 & !q10;
-- Node name is ':12' = 'q11'
-- Equation name is 'q11', location is LC2_B3, type is buried.
q11 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = din0 & din1 & q10 & q11
# din1 & !q10 & !q11
# !din0 & din1 & !q11
# !din1 & !q10 & q11
# !din0 & !din1 & q11
# din0 & !din1 & q10 & !q11;
-- Node name is ':11' = 'q12'
-- Equation name is 'q12', location is LC6_B3, type is buried.
q12 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = din2 & _LC1_B3 & q12
# !din2 & _LC1_B3 & !q12
# !din2 & !_LC1_B3 & q12
# din2 & !_LC1_B3 & !q12;
-- Node name is ':10' = 'q13'
-- Equation name is 'q13', location is LC4_B3, type is buried.
q13 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = din3 & _LC3_B3 & q13
# !din3 & _LC3_B3 & !q13
# !din3 & !_LC3_B3 & q13
# din3 & !_LC3_B3 & !q13;
-- Node name is '|LPM_ADD_SUB:34|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ005);
_EQ005 = din1 & q11
# din0 & q10 & q11
# din0 & din1 & q10;
-- Node name is '|LPM_ADD_SUB:34|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ006);
_EQ006 = _LC1_B3 & q12
# din2 & _LC1_B3
# din2 & q12;
Project Information f:\eda_exercise\cnt4_din\cnt4_din.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,107K
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