txd5.vhd

<CPLDFPGA嵌入式应用开发技术白金手册>配套源代码

--v1.0  data bit 8bit     none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity txd5 is
port
	(indata:in std_logic_vector(7 downto 0);
	 cs,wr,clk:in std_logic;
	 txd,ti:out std_logic);
end txd5;

architecture behav of txd5 is
	signal  sig_count:std_logic_vector(3 downto 0);
	signal  sig_ti,sig_ti1,sig_txd,sig_buffer:std_logic;
	signal  sig_data:std_logic_vector(7 downto 0);
	signal	sig_txddata:std_logic_vector(9 downto 0);
begin
					
process(clk)
begin
	if(clk'event and clk='1')then
		if(cs='0')then
			if(sig_buffer='0')then--发送中断为0，即发送不忙
				if(wr='1')then	--读入数据，准备发送
					for i in 8 downto 1 loop
						sig_txddata(i)<=indata(i-1);--并行输入数据送sig_txddata
					end loop;
					sig_txddata(9)<='0';--加起始位
					sig_txddata(0)<='1';--加偶校验位
				--	sig_data<=indata;
					sig_buffer<='1';
				end if;
			else	--正在发送数据，
				for i in 9 downto 1 loop
					sig_txddata(i)<=sig_txddata(i-1);--数据串行输出
				end loop;
				sig_txd<=sig_txddata(9);

				sig_txddata(0)<='1';--加结束位

				if(sig_count="1000")then--此if语句用于设置ti状态
					sig_count<="0000";
				elsif(sig_count="0000" and sig_ti='1')then
					sig_buffer<='0';
					sig_ti<='0';
				else
					sig_count<=sig_count+'1';
					sig_ti<='1';
				end if;
								
			end if;
		end if;
	end if;
end process;

process  --txd赋值过程
begin
	if(sig_ti='0')then
		txd<='1';
	else
		txd<=sig_txd;
	end if;
end process;

ti<=not sig_ti;
end behav;