entry.s

T－kernel T－monitor Sample

/*""FILE COMMENT""*************************************************************
*       System Name : RENESAS T-Engine, micro T-Engine
*       File Name   : entry.S
*       Version     : 1.00.00
*       Contents    : Reset, interrupt and exception entry routine
*       Model       : SH7727 T-Engine
*       CPU         : SH7727
*       Compiler    : GNU
*       OS          : T-Kernel, T-Kernel/Standard Extension
*       note        : The Software is being delivered to you "AS IS" 
*                   : and Renesas,whether explicitly or implicitly makes  
*                   : no warranty as to its Use or performance. 
*                   : RENESAS AND ITS SUPPLIER DO NOT AND CANNOT WARRANT 
*                   : THE PERFORMANCE OR RESULTS YOU MAY OBTAIN  BY USING 
*                   : THE SOFTWARE. AS TO ANY MATTER INCLUDING WITHOUT 
*                   : LIMITATION NONINFRINGEMENT OF THIRD PARTY RIGHTS,
*                   : MERCHANTABILITY, INTEGRATION, SATISFACTORY QUALITY, 
*                   : OR FITNESS FOR ANY PARTICULAR PURPOSE.
*
*       Copyright (c) 2004 RENESAS TECHNOLOGY CORP. All Rights Reserved.
*       AND RENESAS SOLUTIONS CORP. All Rights Reserved.
*       history     : 2006.02.03 ver.1.00.00
*""FILE COMMENT END""*********************************************************/

	#include <machine.h>
	#include <tk/sysdef.h>
	#include <tk/asm.h>
	#include "tmonitor.h"

/*
 * Peripheral unit/registers
 * addresses are defined in hardware specification
 */
//#define TRA		0xffffffd0
//#define EXPEVT	0xffffffd4
//#define INTEVT2	0xa4000000

/*
 * Vector tables
 * addresses defined are base on T-Monitor implementation specification
 */
#define VECTBL			0x8c000000
#define DEFAULTHDR		0x8c000200	// Trap & interrupt default handler address
#define TLBMISSHDR		0x8c000204


/*
 * Reset handler (0xA0000000)
 */
	.section RESET_HDR, "ax"
	.balign 2
	.globl _reset
	.type _reset, @function
_reset:
	mov.l	TM_START, r0
	jmp	@r0
	nop

		.balign 4
TM_START:	.long 	begin

/* 
 * Any section names and entry routine names can be used.
 * Since they are used only in the Monitor, they can be decided uniquely 
 * in the Monitor
 */

	.section VBRHDR, "ax"
	.globl _exception
	.globl _trapa
	.globl _tlbmiss
	.globl _interrupt
	.type _trapa, @function

/*
 * exception handler (VBR + 0x100)
 */
	.org	0x100
Csym(exception):
	INT_ENTER _exception

	mov.l 	L1_EXPEVT, r0 		// Get exception code
	mov.l 	@r0, r0
	mov 	#-5, r7
	shad 	r7, r0
	shll2 	r0 			// Vector table index

	mov.l 	L1_VECTBL, r7 		// Get handler address
	mov.l 	@(r0,r7), r7
	tst 	r7, r7 			// Undefined if NULL
	bf	l_jmpexc

	mov.l 	L1_DEFAULT, r7 		// Default handler
	mov.l 	@r7, r7

l_jmpexc:
	jmp 	@r7 			// Jump to exception handler
	nop 				// r0 = vector index + factor (0)

/*
 * TRAPA handler
 */
_trapa:
	mov.l 	L1_TRA, r0 		// Get TRAPA index
	mov.l 	@r0, r0

	mov.l 	L1_VECTBL, r7 		// Get handler address
	mov.l 	@(r0,r7), r7
	tst 	r7, r7 			// Undefined if NULL
	bf	l_jmptrap

	mov.l 	L1_DEFAULT, r7 		// Default handler
	mov.l 	@r7, r7

l_jmptrap:
	jmp 	@r7 			// Jump to TRAPA handler
	add 	#1, r0 			// r0 = vector index + factor (1)

		.balign 4
L1_EXPEVT:	.long 	EXPEVT
L1_VECTBL:	.long 	VECTBL
L1_DEFAULT:	.long 	DEFAULTHDR
L1_TRA:		.long	TRA

/*
 * TLB miss exception handler (VBR + 0x400)
 */
	.org	0x400
_tlbmiss:
	mov.l 	L2_TLBMISS, r7 		// Get TLB miss exception handler addr
	mov.l 	@r7, r7

	jmp	@r7 			// Jump to TLB miss exception handler
	nop

		.balign 4
L2_TLBMISS:	.long	 TLBMISSHDR

/*
 * Interrupt handler (VBR + 0x600)
 */
	.org	0x600
_interrupt:
	INT_ENTER _interrupt

	mov.l 	L3_INTEVT2, r0 		// Get interrupt factor
	mov.l 	@r0, r0
	mov 	#-5, r7
	shad 	r7, r0
	shll2 	r0 			// Vector table index

	mov.l 	L3_VECTBL, r7 		// Get handler address
	mov.l 	@(r0,r7), r7
	tst 	r7, r7 			// Undefined if NULL
	bf	l_jmpint

	mov.l 	L3_DEFAULT, r7 		// Default handler
	mov.l 	@r7, r7

l_jmpint:
	jmp 	@r7 			// Jump to interrupt handler
	add 	#2, r0 			// r0 = vector index + factor (2)

		.balign 4
L3_INTEVT2:	.long	INTEVT2
L3_VECTBL:	.long	VECTBL
L3_DEFAULT:	.long	DEFAULTHDR


/*
 * Hardware initialization (VBR + 0x800)
 */
	.org	0x800
begin:
	mov.l	ISP_R6, r6		// init ISP R6 Bank 1 register 
	mov.l	SST_R3, r3		// init System stack R3 Bank 1 register
	mov.l	SPREG, r15		// Initialize SP

	mov.l	VBRREG, r0
	ldc	r0, vbr			// VBR addr set

	mov.l	FRQCR, r1
	mov.w	FRQCR_VAL, r0
	mov.w	r0, @r1

	mov.l	BCR1, r1
	mov.w	BCR1_VAL, r0
	mov.w	r0, @r1			// base control register 1

	mov.l	BCR2, r1
	mov.w	BCR2_VAL, r0
	mov.w	r0, @r1			// base control register 2

	mov.l	WCR1, r1
	mov.w	WCR1_VAL, r0
	mov.w	r0, @r1			// wait state control register 1

	mov.l	WCR2, r1
	mov.w	WCR2_VAL, r0
	mov.w	r0, @r1			// wait state control register 2

	mov.l	MCR, r1
	mov.w	MCR_VAL, r0
	mov.w	r0, @r1			// memory control register

	mov.l	PCR, r1
	mov.w	PCR_VAL, r0
	mov.w	r0, @r1			// PCMCIA control register

	mov.l	RTCSR, r1
	mov.w	RTCSR_DUMMY, r0
	mov.w	r0, @r1			// reflash timer control / status register

	mov.l	RTCNT, r1
	mov.w	RTCNT_VAL, r0
	mov.w	r0, @r1			// reflash timer counter

	mov.l	RTCOR, r1
	mov.w	RTCOR_VAL, r0
	mov.w	r0, @r1			// reflash time constant counter

	mov.l	RFCR, r1
	mov.w	RFCR_VAL, r0
	mov.w	r0, @r1			// reflash count register

	/* SDRAM initalization */
					// 100us dummy wait

	mov.l	SDMR3_ADDR, r1
	mov.w	SDMR3_VAL, r0
	mov.w	r0, @r1			// reflash count register

	mov.l	RTCSR, r1
	mov.w	RTCSR_VAL, r0
	mov.w	r0, @r1			// reflash timer control / status register

					// dummy reflash

	/***********************/

	mov.l	_PINTER, r1		// init PINTER
	mov	#0, r0
	mov.w	r0, @r1

	mov.l	_IPRA, r1		// init IPRA
	mov.w	IPRA_VAL, r0
	mov.w	r0, @r1

	mov.l	_IPRD, r1		// init IPRD
	mov.w	IPRD_VAL, r0
	mov.w	r0, @r1

	mov.l	_IPRG, r1		// init IPRG
	mov.w	IPRG_VAL, r0
	mov.w	r0, @r1

	mov.l	_ICR1, r1		// init ICR1
	mov.w	ICR1_VAL, r0
	mov.w	r0, @r1

	mov.l	_ICR2, r1		// init ICR2
	mov.w	ICR2_VAL, r0
	mov.w	r0, @r1

	mov.l	_PINTER, r1		// init PINTER
	mov.w	PINTER_VAL, r0
	mov.w	r0, @r1

	mov.l	PCCR, r1		// init PCCR
	mov.w	PCCR_VAL, r0
	mov.w	r0, @r1

	mov.l	PDCR, r1		// init PDCR
	mov.w	PDCR_VAL, r0
	mov.w	r0, @r1

	mov.l	PECR, r1		// init PECR
	mov.w	PECR_VAL, r0
	mov.w	r0, @r1

	mov.l	PHCR, r1		// init PHCR
	mov.w	PHCR_VAL, r0
	mov.w	r0, @r1

	mov.l	PJCR, r1		// init PJCR
	mov.w	PJCR_VAL, r0
	mov.w	r0, @r1

	mov.l	PKCR, r1		// init PKCR
	mov.w	PKCR_VAL, r0
	mov.w	r0, @r1

	mov.l	PLCR, r1		// init PLCR
	mov.w	PLCR_VAL, r0
	mov.w	r0, @r1

	mov.l	PMCR, r1		// init PMCR
	mov.w	PMCR_VAL, r0
	mov.w	r0, @r1

	mov.l	SCPCR, r1		// init SCPCR
	mov.w	SCPCR_VAL, r0
	mov.w	r0, @r1

	mov.l	_SYSCONF, r1		// ROMInfo SYSCONF
	mov.l	@r1, r0			// Get the address
	mov.l	SYSCONF, r1
	mov.l	r0, @r1

	mov.l	_DEVCONF, r1		// ROMInfo DEVCONF
	mov.l	@r1, r0			// Get the address
	mov.l	DEVCONF, r1
	mov.l	r0, @r1

	mov.l	ICLK, r1		// init IClk 96 Mhz
	mov.w	ICLK_VAL, r0
	mov.w	r0, @r1

	mov.l	PCLK, r1		// init PCLK 24 Mhz
	mov.w	PCLK_VAL, r0
	mov.w	r0, @r1

	mov.l	RAM_TOP, r1		// init RAM_TOP
	mov.l	RAM_TOP_ADDR, r0
	mov.l	r0, @r1

	mov.l	RAM_END, r1		// init RAM_END
	mov.l	RAM_END_ADDR, r0
	mov.l	r0, @r1

	mov.l	TRAPA_ADDR, r1
	mov.l	TRAPA_HDR, r0
	mov.l	r0, @r1

	mov.l	L8_DEFAULT, r1
	mov.l	DEFAULT_HDR, r0
	mov.l	r0, @r1

	mov.l	MONITOR, r1
	mov.l	MONITOR_HDR, r0
	mov.l	r0, @r1

#if USE_CONSOLE_DRIVER == 0
	mov.l	D_T_MONITOR, r0		// SR initial setting
	ldc	r0, sr
	mov.l	SERIAL_INIT, r0		// init UART st16c2550
	jsr	@r0
	nop
#endif
	mov.l	D_BlockIntSR, r0	// SR initial setting
	ldc	r0, sr

	mov.l	_RESETINIT, r1		// ROMInfo resetinit
	mov.l	@r1, r0			// Get the address
	cmp/eq	#0, r0
	bt	SKIP_RSTINIT
	nop
	jsr	@r0
	nop

SKIP_RSTINIT:
	mov.l	_KERNEL_START, r1	// ROMInfo kernel start
	mov.l	@r1, r0			// Get the address
	jsr	@r0
	nop


/*****************************************************************************/

		.balign 4

/* System shared information */
TRAPA_ADDR:	.long	0x8c00002c
L8_DEFAULT:	.long	DEFAULTHDR
MONITOR:	.long	0x8c0001c0	// T-Monitor Extended SVC handler address
#define _ROMINFO	0x80010000	// ROMInfo base address

_KERNEL_START:	.long	_ROMINFO + 0x04	// ROMInfo kernel start
_RESETINIT:	.long	_ROMINFO + 0x0c	// ROMInfo resetinit
_SYSCONF:	.long	_ROMINFO + 0x78	// ROMInfo SYSCONF
_DEVCONF:	.long	_ROMINFO + 0x7c	// ROMInfo DEVCONF

SYSCONF:	.long	0x8c000268
DEVCONF:	.long	0x8c00026c
ICLK:		.long	0x8c000274
PCLK:		.long	0x8c000276
RAM_TOP:	.long	0x8c000278
RAM_END:	.long	0x8c00027c

FRQCR:		.long	0xffffff80
BCR1:		.long	0xffffff60
BCR2:		.long	0xffffff62
WCR1:		.long	0xffffff64
WCR2:		.long	0xffffff66
MCR:		.long	0xffffff68
PCR:		.long	0xffffff6c
RTCSR:		.long	0xffffff6e
RTCNT:		.long	0xffffff70
RTCOR:		.long	0xffffff72
RFCR:		.long	0xffffff74
SDMR3_ADDR:	.long	0xFFFFE800 + 0x80

_IPRA:		.long	IPRA		// 0xfffffee2 -> sysdef_depend.h
_IPRD:		.long	IPRD		// 0xa4000018 -> sysdef_depend.h
_IPRG:		.long	IPRG		// 0xa4000222 -> sysdef_depend.h
_ICR1:		.long	ICR1		// 0xa4000010 -> sysdef_depend.h
_ICR2:		.long	ICR2		// 0xa4000012 -> sysdef_depend.h
_PINTER:	.long	PINTER		// 0xa4000014 -> sysdef_depend.h
PCCR:		.long	0xa4000104
PDCR:		.long	0xa4000106
PECR:		.long	0xa4000108
PFCR:		.long	0xa400010a
PGCR:		.long	0xa400010c
PHCR:		.long	0xa400010e
PJCR:		.long	0xa4000110
PKCR:		.long	0xa4000112
PLCR:		.long	0xa4000114
PMCR:		.long	0xa4000118
SCPCR:		.long	0x04000116


/* Initialize data */
ISP_R6:		.long	0x8c000500
SST_R3:		.long	0x8c002000
SPREG:		.long	0x8c002000	// T-Monitor stack
VBRREG:		.long	0x80000000	// VBR address

ICLK_VAL:	.long	0x0060		// 96 Mhz
PCLK_VAL:	.long	0x0018		// 24 Mhz
RAM_TOP_ADDR:	.long	0x8c068250
RAM_END_ADDR:	.long	0x8d000000

FRQCR_VAL:	.long	0x0112		// PLL*2, IFC*1, PFC/4
BCR1_VAL:	.long	0x0008
BCR2_VAL:	.long	0x2ae0
WCR1_VAL:	.long	0xaa22
WCR2_VAL:	.long	0xb6dd
MCR_VAL:	.long	0x012c
PCR_VAL:	.long	0x0000
RTCSR_DUMMY:	.long	0xa500		// 
RTCSR_VAL:	.long	0xa518		// CKIO 1/64
RTCNT_VAL:	.long	0xa500
RTCOR_VAL:	.long	0xa50b		// 48MHz /64 14.667us
RFCR_VAL:	.long	0xa400
SDMR3_VAL:	.long	0x00

IPRA_VAL:	.long	0x8000
IPRD_VAL:	.long	0xc000
IPRG_VAL:	.long	0xc000
ICR1_VAL:	.long	0x42aa
ICR2_VAL:	.long	0x000c
PINTER_VAL:	.long	0x000c
PCCR_VAL:	.long	0x0000
PDCR_VAL:	.long	0x0000
PECR_VAL:	.long	0x0500
PFCR_VAL:	.long	0x00AA
PGCR_VAL:	.long	0xA200
PHCR_VAL:	.long	0x0800
PJCR_VAL:	.long	0x0540
PKCR_VAL:	.long	0x0005
PLCR_VAL:	.long	0xaaaa
PMCR_VAL:	.long	0xaa00
SCPCR_VAL:	.long	0x0000

		.balign 4
D_BlockIntSR:	.long	SR_MD | SR_I(15) | SR_RB | SR_BL
D_T_MONITOR:	.long	SR_MD | SR_I(15)

TRAPA_HDR:	.long	_trapa
MONITOR_HDR:	.long	Csym(monitor_svc)
DEFAULT_HDR:	.long	Csym(default_hdr)
#if USE_CONSOLE_DRIVER == 0
SERIAL_INIT:	.long	Csym(init_serial)
#endif