📄 2.txt
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:32:59 11/02/06
// Design Name:
// Module Name: trafficLight2
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module trafficLight2(clk, snCar, ewCar,snRed, snYellow, snGreen,ewRed, ewYellow, ewGreen);
input clk,snCar,ewCar;
output snRed, snYellow, snGreen,ewRed, ewYellow, ewGreen;
reg[5:0] state;
reg snRed,snYellow,snGreen,ewRed, ewYellow, ewGreen;
reg[7:0] count;
//设定count的初始值
initial begin
count = 8'b0;
end
//设定状态值
parameter ewgreen =6'b000001,
ewwait =6'b000010,
ewyellow=6'b000100,
sngreen =6'b001000,
snwait =6'b010000,
snyellow=6'b100000;
always @(posedge clk)
case(state)
ewgreen: begin
ewGreen <= 1;
snRed <= 1;
snYellow<= 0;
snGreen <= 0;
ewRed <= 0;
ewYellow<= 0;
if(count <8'b11000100)
begin
count <= count+1;
if (count==8'b11000100)
begin
state <= ewwait;
count <= 0;
end
end
end
ewwait: begin
if (!snCar)
begin
ewGreen <= 1;
snRed <= 1;
snYellow<= 0;
snGreen <= 0;
ewRed <= 0;
ewYellow<= 0;
end
else state <= ewyellow ;
end
ewyellow: begin
ewYellow <= 1;
snRed <= 1;
snYellow <= 0;
snGreen <= 0;
ewRed <= 0;
ewGreen <= 0;
if(count <8'b00000100)
begin
count <= count+1;
if (count==8'b00000100)
begin
state <= sngreen;
count <= 0;
end
end
end
sngreen: begin
snGreen <= 1;
ewRed <= 1;
snRed <= 0;
snYellow<= 0;
ewYellow<= 0;
ewGreen <= 0;
if(count <8'b11000100)
begin
count <= count+1;
if (count==8'b11000100)
begin
state <= snwait;
count <= 0;
end
end
end
snwait:begin
if (!ewCar)
begin
snGreen <= 1;
ewRed <= 1;
snRed <= 0;
snYellow<= 0;
ewYellow<= 0;
ewGreen <= 0;
end
else state <= snyellow ;
end
snyellow: begin
snYellow <= 1;
ewRed <= 1;
snRed<=0;
snGreen<=0;
ewYellow<=0;
ewGreen<=0;
if(count <8'b00000100)
begin
count <= count+1;
if (count==8'b00000100)
begin
state <= ewgreen;
count <= 0;
end
end
end
default: state <= ewyellow;
endcase
endmodule
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