if_snreg.h

T－kernel Tcp/ip Protocol Stack Sample

#else
#define CONFIG_REG_W    0x00
#endif

#define CR_INT_SEL0     0x0002 /* Interrupt selector */
#define CR_INT_SEL1     0x0004 /* Interrupt selector */
#define CR_DIS_LINK     0x0040 /* Disable 10BaseT Link Test */
#define CR_16BIT        0x0080 /* Bus width */
#define CR_AUI_SELECT   0x0100 /* Use external (AUI) Transceiver */
#define CR_SET_SQLCH    0x0200 /* Squelch level */
#define CR_FULL_STEP    0x0400 /* AUI signalling mode */
#define CR_NOW_WAIT_ST  0x1000 /* Disable bus wait states */

/* The contents of this port are used by the adapter
 * to decode its I/O address.  We use it as a varification
 * that the adapter is detected properly when probing.
 */
#if defined(BUS32)
#define BASE_ADDR_REG_W 0x06 /* The select IO Base addr. */
#else
#define BASE_ADDR_REG_W 0x02 /* The select IO Base addr. */
#endif

/* These registers hold the Ethernet MAC address.
 */
#if defined(BUS32)
#define IAR_ADDR0_REG_W 0x0a /* My Ethernet address */
#define IAR_ADDR1_REG_W 0x0e /* My Ethernet address */
#define IAR_ADDR2_REG_W 0x12 /* My Ethernet address */
#else
#define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */
#define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */
#define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */
#endif

/* General purpose register used for talking to the EEPROM.
 */
#if defined(BUS32)
#define GENERAL_REG_W   0x16
#else
#define GENERAL_REG_W   0x0a
#endif

/* Control register used for talking to the EEPROM and
 * setting some EPH functions.
 */
#if defined(BUS32)
#define CONTROL_REG_W    0x1a
#else
#define CONTROL_REG_W    0x0c
#endif
#define CTR_STORE        0x0001 /* Store something to EEPROM */
#define CTR_RELOAD       0x0002 /* Read EEPROM into registers */
#define CTR_EEPROM_SEL   0x0004 /* Select registers for Reload/Store */
#define CTR_TE_ENABLE    0x0020 /* Enable TX Error detection via EPH_INT */
#define CTR_CR_ENABLE    0x0040 /* Enable Counter Rollover via EPH_INT */
#define CTR_LE_ENABLE    0x0080 /* Enable Link Error detection via EPH_INT */
#define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */
#define CTR_POWERDOWN    0x2000 /* Enter powerdown mode */
#define CTR_RCV_BAD      0x4000 /* Enable receipt of frames with bad CRC */


/* BANK 2
 */

/* Memory Management Unit Control Register
 * Controls allocation of memory to receive and
 * transmit functions.
 */
#if defined(BUS32)
#define MMU_CMD_REG_W   0x02
#else
#define MMU_CMD_REG_W   0x00
#endif
#define MMUCR_BUSY      0x0001 /* MMU busy performing a release */

/* MMU Commands:
 */
#define MMUCR_NOP       0x0000 /* Do nothing */
#define MMUCR_ALLOC     0x0020 /* Or with number of 256 byte packets - 1 */
#define MMUCR_RESET     0x0040 /* Reset MMU State */
#define MMUCR_REMOVE    0x0060 /* Dequeue (but not free) current RX packet */
#define MMUCR_RELEASE   0x0080 /* Dequeue and free the current RX packet */
#define MMUCR_FREEPKT   0x00a0 /* Release packet in PNR register */
#define MMUCR_ENQUEUE   0x00c0 /* Enqueue the packet for transmit */
#define MMUCR_RESETTX   0x00e0 /* Reset transmit queues */
        
/* Packet Number at TX Area
 */
#if defined(BUS32)
#define PACKET_NUM_REG_B   0x07
#else
#define PACKET_NUM_REG_B   0x02
#endif
#if defined(_STD_SH7727_) || defined(_MIC_SH7145_)
#define PACKET_NUM_REG_W   0x02
#endif

/* Packet number resulting from MMUCR_ALLOC
 */
#if defined(BUS32)
#define ALLOC_RESULT_REG_B 0x06
#else
#define ALLOC_RESULT_REG_B 0x03
#endif
#if defined(_STD_SH7727_) || defined(_MIC_SH7145_)
#define ALLOC_RESULT_REG_W 0x02
#endif
#define ARR_FAILED      0x80

/* Transmit and receive queue heads
 */
#if defined(BUS32)
#define FIFO_PORTS_REG_W 0x0a
#else
#define FIFO_PORTS_REG_W 0x04
#endif
#define FIFO_REMPTY     0x8000
#define FIFO_TEMPTY     0x0080
#define FIFO_RX_MASK    0x7f00
#define FIFO_TX_MASK    0x007f

/* The address within the packet for reading/writing.  The
 * PTR_RCV bit is tricky.  When PTR_RCV==1, the packet number
 * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK.
 * When PTR_RCV==0, the packet number to be written is found
 * in the PACKET_NUM_REG_B.
 */
#if defined(BUS32)
#define POINTER_REG_W   0x0e
#else
#define POINTER_REG_W   0x06
#endif
#define PTR_READ        0x2000 /* Intended access mode */
#define PTR_AUTOINC     0x4000 /* Do auto inc after read/write */
#define PTR_RCV         0x8000 /* FIFO_RX is packet, otherwise PNR is packet */

/* Data I/O register to be used in conjunction with
 * The pointer register to read and write data from the
 * card.  The same register can be used for byte and word
 * ops.
 */
#if defined(BUS32)
#define DATA_REG_W      0x12
#else
#define DATA_REG_W      0x08
#endif

#if defined(BUS32)
#define DATA_REG_B      0x13
#else
#define DATA_REG_B      0x08
#endif
#define DATA_1_REG_B    0x08
#define DATA_2_REG_B    0x0a

/* Sense interrupt status (READ)
 */
#if defined(BUS32)
#define INTR_STAT_REG_B 0x1b
#else
#define INTR_STAT_REG_B 0x0c
#endif
#if defined(_STD_SH7727_) || defined(_MIC_SH7145_)
#define INTR_STAT_REG_W 0x0c
#endif

/* Acknowledge interrupt sources (WRITE)
 */
#if defined(BUS32)
#define INTR_ACK_REG_B  0x1b
#else
#define INTR_ACK_REG_B  0x0c
#endif
#if defined(_STD_SH7727_) || defined(_MIC_SH7145_)
#define INTR_ACK_REG_W  0x0c
#endif

/* Interrupt mask.  Bit set indicates interrupt allowed.
 */
#if defined(BUS32)
#define INTR_MASK_REG_B 0x1a
#else
#define INTR_MASK_REG_B 0x0d
#endif
#if defined(_STD_SH7727_) || defined(_MIC_SH7145_)
#define INTR_MASK_REG_W 0x0c
#endif

/* Interrupts
 */
#define IM_RCV_INT      0x01 /* A packet has been received */
#define IM_TX_INT       0x02 /* Packet TX complete */
#define IM_TX_EMPTY_INT 0x04 /* No packets left to TX  */
#define IM_ALLOC_INT    0x08 /* Memory allocation completed */
#define IM_RX_OVRN_INT  0x10 /* Receiver was overrun */
#define IM_EPH_INT      0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */
#define IM_ERCV_INT     0x40 /* not on SMC9192 */
#define IM_MDINT        0x80 /* PHY MI state for SMC91C111 */

/* BANK 3
 */

/* Multicast subscriptions.
 * The multicast handling in the SMC90Cxx is quite complicated.  A table
 * of multicast address subscriptions is provided and a clever way of
 * speeding the search of that table by hashing is implemented in the
 * hardware.  I have ignored this and simply subscribed to all multicasts
 * and let the kernel deal with the results.
 */
#if defined(BUS32)
#define MULTICAST1_REG_W 0x02
#define MULTICAST2_REG_W 0x06
#define MULTICAST3_REG_W 0x0a
#define MULTICAST4_REG_W 0x0e
#else
#define MULTICAST1_REG_W 0x00
#define MULTICAST2_REG_W 0x02
#define MULTICAST3_REG_W 0x04
#define MULTICAST4_REG_W 0x06
#endif

/* These registers do not exist on SMC9192, or at least
 * are not documented in the SMC91C92 data sheet.
 * The REVISION_REG_W register does however seem to work.
 */
#if defined(BUS32)
#define MGMT_REG_W      0x12
#define REVISION_REG_W  0x16 /* (hi: chip id low: rev #) */
#define ERCV_REG_W      0x1a
#else
#define MGMT_REG_W      0x08
#define REVISION_REG_W  0x0a /* (hi: chip id low: rev #) */
#define ERCV_REG_W      0x0c
#endif


/*** Added for PHY setting ***/
#ifdef ORIGINAL
#define MGMT	0x08
#else
#define MGMT	MGMT_REG_W
#endif
#define	MDO	0x01
#define	MDI	0x02
#define	MCLK	0x04
#define	MDOE	0x08
#define MALL    0x0f
#define	OPWrite	0x01
#define	OPRead	0x02

/* Reg.0 Control */
#define PHY_CNTL_REG      0x00
#define PHY_CNTL_RST      0x8000
#define PHY_CNTL_LPBK     0x4000
#define PHY_CNTL_SPEED    0x2000
#define PHY_CNTL_ANEG_EN  0x1000
#define PHY_CNTL_PDN      0x0800
#define PHY_CNTL_MII_DIS  0x0400
#define PHY_CNTL_ANEG_RST 0x0200
#define PHY_CNTL_DPLX     0x0100
#define PHY_CNTL_COLST    0x0080

/* Reg.1 Status */
#define PHY_STS_REG       0x01
#define PHY_STS_CAP_T4    0x8000
#define PHY_STS_CAP_TXF   0x4000
#define PHY_STS_CAP_TXH   0x2000
#define PHY_STS_CAP_TF    0x1000
#define PHY_STS_CAP_TH    0x0800
#define PHY_STS_CAP_SUPR  0x0040
#define PHY_STS_ANEG_ACK  0x0020
#define PHY_STS_REM_FLT   0x0010
#define PHY_STS_CAP_ANEG  0x0008
#define PHY_STS_LINK      0x0004
#define PHY_STS_JAB       0x0002
#define PHY_STS_EXREG     0x0001

/* Reg.18 Status Output and Reg.19 Mask */
#define PHY_INT_REG       0x12	/* Status Output */
#define PHY_MASK_REG      0x13	/* Interrupt Mask */
#define PHY_INT_INT       0x8000	/* Ints bits have changed */
#define PHY_INT_LNKFAIL   0x4000	/* Link not detect */
#define PHY_INT_LOSSSYNC  0x2000	/* Descrambler has lost sync. */
#define PHY_INT_CWRD      0x1000	/* Invalid 4B5B code detected */
#define PHY_INT_SSD       0x0800	/* No start of stream delimiter detected */
#define PHY_INT_ESD       0x0400	/* No end of stream delimiter detected */
#define PHY_INT_RPOL      0x0200	/* Reverse polarity detected */
#define PHY_INT_JAB       0x0100	/* Jabber detected */
#define PHY_INT_SPDDET    0x0080	/* 100Base-TX(=1), 10Base-T(=0) */
#define PHY_INT_DPLXDET   0x0040	/* Full duplex(=1), Half duplex(=0) */

/* These are constants expected to be found in the
 * chip id register.
 */
#define CHIP_9190       3
#define CHIP_9194       4
#define CHIP_9195       5
#define CHIP_91100      7

static const char * chip_ids[ 15 ] =  {
         NULL, NULL, NULL,
 /* 3 */ "SMC91C90/91C92",
 /* 4 */ "SMC91C94",
 /* 5 */ "SMC91C95",
         NULL,
 /* 7 */ "SMC91C100",
         NULL,
 /* 9 */ "SMC91C111",
		NULL, NULL,
         NULL, NULL, NULL
};


/* When packets are stuffed into the card or sucked out of the card
 * they are set up more or less as follows:
 *
 * Addr msbyte   lsbyte
 * 00   SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status
 * 02   RRRRR             - RESERVED (unused)
 * 02        CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored)
 * 04   DDDDDDDD DDDDDDDD - DESTINATION ADDRESS
 * 06   DDDDDDDD DDDDDDDD        (48 bit Ethernet MAC Address)
 * 08   DDDDDDDD DDDDDDDD
 * 0A   SSSSSSSS SSSSSSSS - SOURCE ADDRESS
 * 0C   SSSSSSSS SSSSSSSS        (48 bit Ethernet MAC Address)
 * 0E   SSSSSSSS SSSSSSSS
 * 10   PPPPPPPP PPPPPPPP
 * ..   PPPPPPPP PPPPPPPP
 * C-2  CCCCCCCC          - CONTROL BYTE
 * C-2           PPPPPPPP - Last data byte (If odd length)
 *
 * The STATUS_WORD is derived from the EPH_STATUS_REG_W register
 * during transmit and is composed of another set of bits described
 * below during receive.
 */


/* Receive status bits.  These values are found in the status word
 * field of a received packet.  For receive packets I use the RS_ODDFRAME
 * to detect whether a frame has an extra byte on it.  The CTLB_ODD
 * bit of the control byte tells the same thing.
 */
#define RS_MULTICAST    0x0001 /* Packet is multicast */
#define RS_HASH_MASK    0x007e /* Mask of multicast hash value */
#define RS_TOOSHORT     0x0400 /* Frame was a runt, <64 bytes */
#define RS_TOOLONG      0x0800 /* Frame was giant, >1518 */
#define RS_ODDFRAME     0x1000 /* Frame is odd lengthed */
#define RS_BADCRC       0x2000 /* Frame had CRC error */
#define RS_ALGNERR      0x8000 /* Frame had alignment error */
#define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)

#define RLEN_MASK       0x07ff /* Significant length bits in RX length */

/* The control byte has the following significant bits.
 * For transmit, the CTLB_ODD bit specifies whether an extra byte
 * is present in the frame.  Bit 0 of the byte count field is
 * ignored.  I just pad every frame to even length and forget about
 * it.
 */
#define CTLB_CRC        0x10 /* Add CRC for this packet (TX only) */
#define CTLB_ODD        0x20 /* The packet length is ODD */


/*
 * I define some macros to make it easier to do somewhat common
 * or slightly complicated, repeated tasks.
 */

/* The base I/O address.
 */
#define BASE    (sc->sn_io_addr)

/* Select a register bank, 0 to 3
 */
#define SMC_SELECT_BANK(x)  { outw( BASE + BANK_SELECT_REG_W, (x) ); }

/* Define a small delay for the reset
 */
#define SMC_DELAY() { inw( BASE + RECV_CONTROL_REG_W );\
                      inw( BASE + RECV_CONTROL_REG_W );\
                      inw( BASE + RECV_CONTROL_REG_W );  }

struct isa_device {
  int     id_iobase;      /* base i/o address */
  int     id_irq;         /* interrupt request */
  int     id_unit;        /* unit number */
};

#endif  /* _IF_SNREG_H_ */