if_snreg.h

T－kernel Tcp/ip Protocol Stack Sample

/****************************************************************************
 * Copyright (C) 2001-2006 MITSUBISHI ELECTRIC CORPORATION and
 * RENESAS SOLUTIONS CORPORATION and
 * RENESAS TECHNOLOGY CORPORATION
 * All rights reserved.
 *
 ****************************************************************************
 * Copyright (c) 1996 Gardner Buchanan <[e-mail]>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Gardner Buchanan.
 * 4. The name of Gardner Buchanan may not be used to endorse or promote
 *    products derived from this software without specific prior written
 *    permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *   $Id: if_snreg.h,v 1.1 2001/10/11 05:41:25 inui Exp $
 */

/*
 * This file contains register information and access macros for
 * the SMC91xxx chipset.
 *
 * Information contained in this file was obtained from the SMC91C92
 * and SMC91C94 manuals from SMC.  You will need one of these in order
 * to make any meaningful changes to this driver.  Information about
 * obtaining one can be found at http://www.smc.com in the components
 * division.
 *
 * This FreeBSD driver is derived in part from the smc9194 Linux driver
 * by Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
 * It is also derived in part from the FreeBSD ep (3C509) driver which
 * is Copyright (c) 1993 Herb Peyerl ([e-mail]) All rights
 * reserved.
 *
 */
#ifndef _IF_SNREG_H_
#define _IF_SNREG_H_

#if defined(_MIC_SH7145_)
/* base address of LAN Controller space */
#define SMC_LAN_BASEADDR 0x00C00300

/* LAN interrupt definition number */
#if defined(T_KERNEL)
#define SMC_LAN_IRQ 0x2B	/* interrupt vector number for IRQ3 */
#endif

/*
 * PFC(Pin Function Controller) register
 *   NOTE: we use in_h()/out_h() to access these regs.
 */
#define PACRL2	0xFFFF838E
#define PBCR2	0xFFFF839A
#define PDCRL1	0xFFFF83AC
#define PDCRL2	0xFFFF83AE

/*
 * BSC(Bus State Controller) register
 *   NOTE: we use in_h()/out_h() to access these regs.
 */
#define BCR1	0xFFFF8620
#define BCR2	0xFFFF8622
#define WCR1	0xFFFF8624

/*
 * INTC register
 *   NOTE: we use in_h()/out_h() to access these regs.
 */
#define ICR1	0xFFFF8358
#define ICR2	0xFFFF8366
#define ISR	0xFFFF835A
#define IPRA	0xFFFF8348
#endif /* _MIC_SH7145_ */

#if defined(_STD_SH7727_)
/* base address of LAN Controller space */
/* CS4 = H'1000 0000 (physical addr) <-> H'B000 0000 (logical addr) */
#define SMC_LAN_BASEADDR 0xB0000300

/* LAN interrupt definition number */
#if defined(T_KERNEL)
#define SMC_LAN_IRQ 0x2A0	/* exception code (EXPEVT/INTEVT2) */
#endif

/*
 * PFC(Pin Function Controller) register
 *   NOTE: we use in_h()/out_h() to access these regs.
 */
#define PHCR	0xA400010E
#define PKCR	0xA4000112

/*
 * BSC(Bus State Controller) register
 *   NOTE: we use in_h()/out_h() to access these regs.
 */
#define BCR2	0xFFFFFF62
#define WCR1	0xFFFFFF64
#define WCR2	0xFFFFFF66

/*
 * INTC register
 *   NOTE: we use in_h()/out_h() to access these regs.
 */
#define ICR1	0xA4000010
#define IPRC	0xA4000016
#endif /* _STD_SH7727_ */

#if defined(_MIC_M32104_)
/* base address of LAN Controller space */
#define SMC_LAN_BASEADDR 0x01000300

/* LAN interrupt definition number */
#if defined(T_KERNEL)
#define SMC_LAN_IRQ 0x15	/* interrupt vector number */
#endif

/* ICU register */
#define ICUCR1 ( *((volatile unsigned int *)0x007FF200) )
#endif /* _MIC_M32104_ */

#if defined(_MIC_M32192_)
/* base address of LAN Controller space */
#define SMC_LAN_BASEADDR 0x01000300

/* LAN interrupt definition number */
#if defined(T_KERNEL)
#define SMC_LAN_IRQ 0x2	/* interrupt vector number */
#endif

#endif /* _MIC_M32192_ */


#if defined(LAN91C111)
/*
 * Maximum size of SRAM is 8KB (in case of 91C111),
 * minimum size of transmission buffer is no need,
 * and page size is 2KB.
 * Hence SN_MAX_RECV_COUNT = (8192 / 2048) = 4.
 */
#define SN_MAX_RECV_COUNT 4
#else
/*
 * Maximum size of SRAM is 128KB (in case of 91C100FD),
 * minimum size of transmission buffer is 2x2KB,
 * and page size is 2KB.
 * Hence SN_MAX_RECV_COUNT = ((131072 - 2048 * 2) / 2048) = 62.
 */
#define SN_MAX_RECV_COUNT 62
#endif

#define SMC_LAN_0 0

#if defined(LAN91C111)
/* for chip bug */
#define PHY_ADDR 0
#else
#define PHY_ADDR 2
#endif

/*
 * Ethernet software status per interface.  The first element MUST
 * be the arpcom struct since the address of the arpcom struct is
 * used as a backdoor to obtain the address of this whole structure
 * in many cases.
 */
struct sn_softc {
    struct arpcom arpcom;       /* Ethernet common part */
    unsigned int sn_io_addr;    /* i/o bus address (BASE) */
    int pages_wanted;           /* Size of outstanding MMU ALLOC */
    int intr_mask;              /* Most recently set interrupt mask */
    caddr_t bpf;                /* BPF  "magic cookie" */
#if defined(LAN91C111)
    unsigned short lastPhy18;   /* PHY status output(PHY reg.18) */
#endif
};

/*
 * Some global constants
 */
#define ETHER_MIN_LEN        64
#define ETHER_MAX_LEN      1518
#define ETHER_ADDR_LEN        6



/*
 * Wait time for memory to be free.  This probably shouldn't be
 * tuned that much, as waiting for this means nothing else happens
 * in the system
 */
#define MEMORY_WAIT_TIME 32


/* The SMC91xxx uses 16 I/O ports
 */
#define SMC_IO_EXTENT   16


/*
 * A description of the SMC registers is probably in order here,
 * although for details, the SMC datasheet is invaluable.
 * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet
 * Controller With RAM", Rev. 12/0/94.  Constant definitions I give
 * here are loosely based on the mnemonic names given to them in the
 * data sheet, but there are many exceptions.
 *
 * Basically, the chip has 4 banks of registers (0 to 3), which
 * are accessed by writing a number into the BANK_SELECT register
 * (I also use a SMC_SELECT_BANK macro for this).  Registers are
 * either Byte or Word sized.  My constant definitions end in _B
 * or _W as appropriate.
 *
 * The banks are arranged so that for most purposes, bank 2 is all
 * that is needed for normal run time tasks.
 */

/*
 * Bank Select Register.  This also doubles as
 * a chip identification register.  This register
 * is mapped at the same position in all banks.
 */
#if defined(BUS32)
#define BANK_SELECT_REG_W       0x1e
#else
#define BANK_SELECT_REG_W       0x0e
#endif
#define BSR_DETECT_MASK         0xff00
#define BSR_DETECT_VALUE        0x3300


/* BANK 0
 */

/* Transmit Control Register controls some aspects of the transmit
 * behavior of the Ethernet Protocol Handler.
 */
#if defined(BUS32)
#define TXMIT_CONTROL_REG_W  0x02
#else
#define TXMIT_CONTROL_REG_W  0x00
#endif

#define TCR_ENABLE      0x0001  /* if this is 1, we can transmit */
#define TCR_LOOP        0x0002  /* Enable internal analogue loopback */
#define TCR_FORCOL      0x0004  /* Force Collision on next TX */
#define TCR_PAD_ENABLE  0x0080  /* Pad short packets to 64 bytes */
#define TCR_NOCRC       0x0100  /* Do not append CRC */
#define TCR_MON_CSN     0x0400  /* monitors the carrier status */
#define TCR_FDUPLX      0x0800  /* receive packets sent out */
#define TCR_STP_SQET    0x1000  /* stop transmitting if Signal quality error */
#define TCR_EPH_LOOP    0x2000  /* Enable internal digital loopback */

#define TCR_SWFDUP      0x8000  /* Enable switched Full Duplex mode */


/* Status of the last transmitted frame and instantaneous status of
 * the Ethernet Protocol Handler jumbled together.  In auto-release
 * mode this information is simply discarded after each TX.  This info
 * is copied to the status word of in-memory packets after transmit
 * where relevent statuses can be checked.
 */
#if defined(BUS32)
#define EPH_STATUS_REG_W 0x06
#else
#define EPH_STATUS_REG_W 0x02
#endif

#define EPHSR_TX_SUC    0x0001 /* Transmit was successful */
#define EPHSR_SNGLCOL   0x0002 /* Single collision occurred */
#define EPHSR_MULCOL    0x0004 /* Multiple Collisions occurred */
#define EPHSR_LTX_MULT  0x0008 /* Transmit was a multicast */
#define EPHSR_16COL     0x0010 /* 16 Collisions occurred, TX disabled */
#define EPHSR_SQET      0x0020 /* SQE Test failed, TX disabled */
#define EPHSR_LTX_BRD   0x0040 /* Transmit was a broadcast */
#define EPHSR_DEFR      0x0080 /* TX deferred due to carrier det. */
#define EPHSR_LATCOL    0x0200 /* Late collision detected, TX disabled */
#define EPHSR_LOST_CAR  0x0400 /* Lost carrier sense, TX disabled */
#define EPHSR_EXC_DEF   0x0800 /* Excessive deferrals in TX >2 MAXETHER times */
#define EPHSR_CTR_ROL   0x1000 /* Some ECR Counter(s) rolled over */
#define EPHSR_RX_OVRN   0x2000 /* Receiver overrun, packets dropped */
#define EPHSR_LINK_OK   0x4000 /* Link integrity is OK */
#define EPHSR_TXUNRN    0x8000 /* Transmit underrun */


/* Receiver Control Register controls some aspects of the receive
 * behavior of the Ethernet Protocol Handler.
 */
#if defined(BUS32)
#define RECV_CONTROL_REG_W 0x0a
#else
#define RECV_CONTROL_REG_W 0x04
#endif

#define RCR_RX_ABORT    0x0001 /* Received huge packet */
#define RCR_PROMISC     0x0002 /* enable promiscuous mode */
#define RCR_ALMUL       0x0004 /* receive all multicast packets */
#define RCR_ENABLE      0x0100 /* IFF this is set, we can recieve packets */
#define RCR_STRIP_CRC   0x0200 /* strips CRC */
#define RCR_GAIN_BITS   0x0c00 /* PLL Gain control (for testing) */
#define RCR_FILT_CAR    0x4000 /* Enable 12 bit carrier filter */
#define RCR_SOFTRESET   0x8000 /* Resets the EPH logic */       


/* TX Statistics counters
 */
#if defined(BUS32)
#define COUNTER_REG_W   0x0e
#else
#define COUNTER_REG_W   0x06
#endif

#define ECR_COLN_MASK   0x000f /* Vanilla collisions */
#define ECR_MCOLN_MASK  0x00f0 /* Multiple collisions */
#define ECR_DTX_MASK    0x0f00 /* Deferred transmits */
#define ECR_EXDTX_MASK  0xf000 /* Excessively deferred transmits */

/* Memory Information
 */
#if defined(BUS32)
#define MEM_INFO_REG_W  0x12
#else
#define MEM_INFO_REG_W  0x08
#endif

#define MIR_FREE_MASK   0xff00 /* Free memory pages available */
#define MIR_TOTAL_MASK  0x00ff /* Total memory pages available */

/* Memory Configuration
 */
#if defined(BUS32)
#define MEM_CFG_REG_W   0x16
#else
#define MEM_CFG_REG_W   0x0a
#endif

#define MCR_TXRSV_MASK  0x001f /* Count of pages reserved for transmit */

#if defined(LAN91C111)
/* Receive/Phy Control
 */
#if defined(BUS32)
#define PHY_CONTROL_REG_W   0x16
#else
#define PHY_CONTROL_REG_W   0x0a
#endif

#define RPCR_SPEED	0x2000
#define RPCR_DPLX	0x1000
#define RPCR_ANEG	0x0800
#define RPCR_LS2A	0x0080
#define RPCR_LS1A	0x0040
#define RPCR_LS0A	0x0020
#define RPCR_LS2B	0x0010
#define RPCR_LS1B	0x0008
#define RPCR_LS0B	0x0004

#define RPCR_DEFAULT	(RPCR_ANEG | RPCR_LS2A | RPCR_SPEED | RPCR_DPLX)
#endif /* LAN91C111 */

/* Bank 0, Register 0x0c is unised in the SMC91C92
 */


/* BANK 1
 */

/* Adapter configuration
 */
#if defined(BUS32)
#define CONFIG_REG_W    0x02