sci_cpudef.h

T－Kernel Driver Sample

/*""FILE COMMENT""*************************************************************
*       System Name : RENESAS T-Engine/micro T-Engine
*       File Name   : sci_cpudef.h 
*       Version     : 1.00.00
*       Contents    : SCI data definition depend on CPU
*       Model       : SH7145 micro T-Engine
*       CPU         : SH7145F
*       Compiler    : GNU/Renesas SH-C
*       OS          : T-Kernel
*       note        : The Software is being delivered to you "AS IS" 
*                   : and Renesas,whether explicitly or implicitly makes  
*                   : no warranty as to its Use or performance. 
*                   : RENESAS AND ITS SUPPLIER DO NOT AND CANNOT WARRANT 
*                   : THE PERFORMANCE OR RESULTS YOU MAY OBTAIN  BY USING 
*                   : THE SOFTWARE. AS TO ANY MATTER INCLUDING WITHOUT 
*                   : LIMITATION NONINFRINGEMENT OF THIRD PARTY RIGHTS,
*                   : MERCHANTABILITY, INTEGRATION, SATISFACTORY QUALITY, 
*                   : OR FITNESS FOR ANY PARTICULAR PURPOSE.
*
*       Copyright (c) 2005 RENESAS TECHNOLOGY CORP. All Rights Reserved.
*       AND RENESAS SOLUTIONS CORP. All Rights Reserved.
*       history   : 2005.01.11 ver1.00.00
*""FILE COMMENT END""*********************************************************/

#ifndef	_SCI_CPUDEF_H_
#define	_SCI_CPUDEF_H_

#ifndef _SCI_CPUDEF_C_
IMPORT const UW sci_int_tbl[];
IMPORT const UW sci_reg_tbl[];
IMPORT const UW sci_ipr_adr_tbl[];
IMPORT const UW sci_ipr_ofs_tbl[];
#endif

#define SCI_PORT_MAX	(4)	/* max port number */

/* interrupt number */
#define INT_ERI(p)	(UW)(sci_int_tbl[p] + 0x00)
#define INT_RXI(p)	(UW)(sci_int_tbl[p] + 0x01)
#define INT_TXI(p)	(UW)(sci_int_tbl[p] + 0x02)
#define INT_TEI(p)	(UW)(sci_int_tbl[p] + 0x03)

/* SCI registers */
#if 1
#define REG_SMR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x00))
#define REG_BRR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x01))
#define REG_SCR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x02))
#define REG_SCR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x02))
#define REG_TDR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x03))
#define REG_SSR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x04))
#define REG_RDR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x05))
#define REG_SDCR(p)	(*(volatile UB*)(sci_reg_tbl[p] + 0x06))
#else
#define REG_SMR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x00))
#define REG_BRR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x01))
#define REG_SCR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x02))
#define REG_SCR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x02))
#define REG_TDR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x03))
#define REG_SSR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x04))
#define REG_RDR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x05))
#define REG_SDCR(p)	(UB)(*(volatile UB*)(sci_reg_tbl[p] + 0x06))
#endif

#define SMR_CHR		(0x40)
#define SMR_PE		(0x20)
#define SMR_OE		(0x10)
#define SMR_STOP	(0x08)
#define SMR_CKS0	(0x02)
#define SMR_CKS1	(0x01)

#define SCR_TIE		(0x80)
#define SCR_RIE		(0x40)
#define SCR_TE		(0x20)
#define SCR_RE		(0x10)
#define SCR_TEIE	(0x04)

#define SSR_TDRE	(0x80)
#define SSR_RDRF	(0x40)
#define SSR_ORER	(0x20)
#define SSR_FER		(0x10)
#define SSR_PER		(0x08)
#define SSR_TEND	(0x04)

#define SCR_INIT	(0x00)
#define SMR_INIT	(0x00)

#define SET_BRCNT(n,c)	\
	REG_BRR(n) = ((c) & 0xff); \
	REG_SMR(n) = ((c) >> 8) | SMR_INIT;

/* BRCNT for P=25MHz (uT-Engine) */
#define BRCNT_300	(0x0250)
#define BRCNT_600	(0x01A2)
#define BRCNT_1200	(0x0150)
#define BRCNT_2400	(0x0128)
#define BRCNT_4800	(0x00A2)
#define BRCNT_9600	(0x0050)
#define BRCNT_19200	(0x0028)
#define BRCNT_38400	(0x0013)
#define BRCNT_115200	(0x0006)

/* BRCNT for P=22MHz */
// #define BRCNT_300	(0x0247)
// #define BRCNT_600	(0x018E)
// #define BRCNT_1200	(0x0147)
// #define BRCNT_2400	(0x0123)
// #define BRCNT_4800	(0x008E)
// #define BRCNT_9600	(0x0047)
// #define BRCNT_19200	(0x0023)
// #define BRCNT_38400	(0x0011)
// #define BRCNT_115200	(0x0005)

/* INTC registers */
#define REG_IPRA	(0xffff8348)
#define REG_IPRB	(0xffff834a)
#define REG_IPRC	(0xffff834c)
#define REG_IPRD	(0xffff834e)
#define REG_IPRE	(0xffff8350)
#define REG_IPRF	(0xffff8352)
#define REG_IPRG	(0xffff8354)
#define REG_IPRH	(0xffff8356)
#define REG_IPRI	(0xffff835c)
#define REG_IPRJ	(0xffff835e)

#define SCI_INT_LEVEL	(14)

#define SET_INTLV(p,lv) \
	*((UH*)sci_ipr_adr_tbl[p]) = \
	  ( *((UH*)sci_ipr_adr_tbl[p]) & (0x000f << sci_ipr_ofs_tbl[p]) ) | \
	  ( (lv) << sci_ipr_ofs_tbl[p])

#endif /* _SCI_CPUDEF_H_ */