counter.vhd

来自「fpga介绍及其相关实验代码」· VHDL 代码 · 共 48 行

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity counter is
	generic (
	MAX_COUNT : integer := 10 );
	port (
	clk : in std_logic;
	reset_n : in std_logic;
	ce : in std_logic;
	overflow : out std_logic );
end counter;

--}} End of automatically maintained section
-- 结构体
architecture counter of counter is

signal count : integer;

begin

	-- enter your statements here --
	-- 主过程
	main: process( clk, reset_n )
	begin
		-- 判断复位信号
		if reset_n = '0' then
			count <= 0;
			overflow <= '0';
		-- 时钟信号的上升沿动作
		elsif rising_edge(clk) and ce = '1' then
			-- 在计数上阈时候输出提示信号overflow
			if count = MAX_COUNT-1 then
				count <= 0;
				overflow <= '1';
			-- 恢复提示信号overflow为低
			elsif count = 0 then
				count <= count+1;
				overflow <= '0';
			else
				count <= count+1;
			end if;
		end if;
	end process;

end counter;