lcd_init0504.v

液晶显示驱动源程序代码

		
		28:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		29:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		30:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		31:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		32:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		33:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		34:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		35:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		36:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		37:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		38:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		39:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		40:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		41:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		42:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		43:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		44:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		45:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		46:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		47:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		48:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		49:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		50:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		51:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		52:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		53:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		default:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
	endcase
	end
endmodule

/*		
		
//generate a counter && number
always@ (posedge clock or negedge reset)
begin
	if(!reset)
	begin
		counter<=0;
		number<=0;
		sclk<=0;
	end
	else //if(enable)
	begin
		if(counter< 48)
		begin
			sclk<=~sclk;                                 //generate sclk
			counter<=counter + 1'b1;
		end
		else if(counter<53)
			begin
				counter<=counter+1'b1;
				sclk<=1;
			end
			else
			
				begin
				counter<=0;
			    if(number<=1000)
				number<=number+1'b1;
				else
				number<=0;
				end
	end
end

//generate signal "cs"
always@ (posedge clock or negedge reset)
begin
  if(!reset)
    cs <=1;
  else if(counter>= 0 && counter <= 48)
    cs <= 0;
		else
    cs <= 1;
end
*/










/*
initial
begin
        count = 1;
		while(reset);
		while(!reset);
		cs=0;
        while (count < 53) 
		begin
			if(count==4)
				begin
					data_tmp=command[count];
					flag_command=1;
					while(cs==0);
					cs=0;
					data_tmp=data[count];
					flag_command=0;
					flag_20ms=1;
					while(flag_20ms);
					count=count+1;
				end
              else if(count==17)
				begin
					data_tmp=command[count];
					flag_command=1;
					while(cs==0);
					cs=0;
					data_tmp=data[count];
					flag_command=0;
					flag_200ms=1;
					while(flag_200ms);
					count=count+1;
				end
			 else if((count==19) | (count==20) | (count==23))
				begin
					data_tmp=command[count];
					flag_command=1;
					while(cs==0);
					cs=0;
					data_tmp=data[count];
					flag_command=0;
					flag_200ms=1;
					while(flag_200ms);
					count=count+1;
				end
			else if(count==52)
				begin
					data_tmp=command[count];
					flag_command=1;
					while(cs==0);
					cs=0;
					data_tmp=data[count];
					flag_command=0;
					flag_10ms=1;
					while(flag_10ms);
					count=count+1;
				end
			else
				begin
					data_tmp=command[count];
					flag_command=1;
					while(cs==0);
					cs=0;
					data_tmp=data[count];
					flag_command=0;
					count=count+1;
				end
				end
end
*/
		
		
//delay 20ms
/*
always@ (posedge clock or negedge reset)
begin
	if(!reset)
		begin
			clk_cnt_20<=0;
			flag_20ms=0;
		end
	else if(flag_20ms)
		begin
			if(clk_cnt_20==(500000-1))
				begin
				clk_cnt_20<=0;
				flag_20ms=0;
				end
			else
			clk_cnt_20<=clk_cnt_20+1;
		end
			else clk_cnt_20=0;
end
*/

//delay 10ms
/*
always@ (posedge clock or negedge reset)
begin
	if(!reset)
		begin
			clk_cnt_10<=0;
			flag_10ms=0;
		end
	else if(flag_10ms)
		begin
			if(clk_cnt_10==(250000-1))
				begin
				clk_cnt_10<=0;
				flag_10ms=0;
				end
			else
			clk_cnt_10<=clk_cnt_10+1;
		end
			else clk_cnt_10=0;
end
*/

//delay 50ms
/*
always@ (posedge clock or negedge reset)
begin
	if(!reset)
		begin
			clk_cnt_50<=0;
			flag_50ms=0;
		end
	else if(flag_50ms)
		begin
			if(clk_cnt_50==(1250000-1))
				begin
				clk_cnt_50<=0;
				flag_50ms=0;
				end
			else
			clk_cnt_50<=clk_cnt_50+1;
		end
			else clk_cnt_50=0;
end
*/

//delay 200ms
/*
always@ (posedge clock or negedge reset)
begin
	if(!reset)
		begin
			clk_cnt_200<=0;
			flag_200ms=0;
		end
	else if(flag_200ms)
		begin
			if(clk_cnt_200==(5000000-1))
				begin
				clk_cnt_200<=0;
				flag_200ms=0;
				end
			else
			clk_cnt_200<=clk_cnt_200+1;
		end
			else clk_cnt_200=0;
end
*/
//Generate "sclk"
//always@ (posedge clock or negedge reset)
//begin
	//if(!reset)
	//sclk=1;
	//else
	//sclk=clock;
/*begin
  case(counter)
    6'd02: sclk = 1;
    6'd05: sclk = 1;
    6'd08: sclk = 1;
    6'd11: sclk = 1;
    6'd14: sclk = 1;
    6'd17: sclk = 1;
    6'd20: sclk = 1;
    6'd23: sclk = 1;
    6'd26: sclk = 1;
    6'd29: sclk = 1;
    6'd32: sclk = 1;
    6'd35: sclk = 1;
    6'd38: sclk = 1;
    6'd41: sclk = 1;
    6'd44: sclk = 1;
    6'd47: sclk = 1;
    default sclk = 0;
endcase
*/
//end
/*
always@ (number or cs)
begin
  if(cs == 0)
  case(number)

    9'd01:index<= 8'd00;
    9'd02:index <= 8'd01;
    9'd03:index <= 8'd02;
    9'd04:index <= 8'd03;
//delay 20
    9'd24:index <= 8'd04;
    9'd25:index <= 8'd05;
    9'd26:index <= 8'd06;
    9'd27:index <= 8'd07;
    9'd28:index <= 8'd08;
    9'd29:index <= 8'd09;
    9'd30:index <= 8'd10;
    9'd31:index <= 8'd11;
    9'd32:index <= 8'd12;
    9'd33:index <= 8'd13;
    9'd34:index <= 8'd14;
    9'd35:index <= 8'd15;
    9'd36:index <= 8'd16;
//delay 200
    9'd236:index <= 8'd17;
    9'd237:index <= 8'd18;
//delay 50
    9'd287:index <= 8'd19;
//delay 50
	9'd337:index <= 8'd20;
    9'd338:index <= 8'd21;
    9'd339:index <= 8'd22;
//delay 50
    9'd389:index <= 8'd23;
    9'd390:index <= 8'd24;
    9'd391:index <= 8'd25;
    9'd392:index <= 8'd26;
    9'd393:index <= 8'd27;
    9'd394:index <= 8'd28;
    9'd395:index <= 8'd29;
    9'd396:index <= 8'd30;
    9'd397:index <= 8'd31;
    9'd398:index <= 8'd32;
    9'd399:index <= 8'd33;
    9'd400:index <= 8'd34;
    9'd401:index <= 8'd35;
	9'd402:index <= 8'd36;
    9'd403:index <= 8'd37;
    9'd404:index <= 8'd38;
    9'd405:index <= 8'd39;
    9'd406:index <= 8'd40;
    9'd407:index <= 8'd41;
    9'd408:index <= 8'd42;
    9'd409:index <= 8'd43;
    9'd410:index <= 8'd44;
    9'd411:index <= 8'd45;
    9'd412:index <= 8'd46;
    9'd413:index <= 8'd47;
    9'd414:index <= 8'd48;
    9'd415:index <= 8'd49;
    9'd416:index <= 8'd50;
    9'd417:index <= 8'd51;
//delay 10
    9'd427:index <= 8'd52;
    default:index<= 8'd00;
  endcase
  else
    index <= 8'd00;
end
*/

//assign sdi=data[index];
//assign sdi=command[index];


/*
always@(posedge sclk )
if(number%2!=0)
begin
case(counter)//0x70
	8'd1:sdi<=1'b0;
	8'd3:sdi<=1'b1;
	8'd5:sdi<=1'b1;
	8'd7:sdi<=1'b1;
	8'd9:sdi<=1'b0;
	8'd11:sdi<=1'b0;
	8'd13:sdi<=1'b0;
	8'd15:sdi<=1'b0;
	
	8'd17:sdi<=(command[index]>>15);
	8'd19:sdi<=(command[index]>>14);
	8'd21:sdi<=(command[index]>>13);
	8'd23:sdi<=(command[index]>>12);
	8'd25:sdi<=(command[index]>>11);
	8'd27:sdi<=(command[index]>>10);
	8'd29:sdi<=(command[index]>>9);
	8'd31:sdi<=(command[index]>>8);
	8'd33:sdi<=(command[index]>>7);
	8'd35:sdi<=(command[index]>>6);
	8'd37:sdi<=(command[index]>>5);
	8'd39:sdi<=(command[index]>>4);
	8'd41:sdi<=(command[index]>>3);
	8'd43:sdi<=(command[index]>>2);
	8'd45:sdi<=(command[index]>>1);
	8'd47:sdi<=(command[index]>>0);
	default:  sdi<=0;
endcase
end
else
begin
case(counter)//0x72
	8'd1:sdi<=1'b0;
	8'd3:sdi<=1'b1;
	8'd5:sdi<=1'b1;
	8'd7:sdi<=1'b1;
	8'd9:sdi<=1'b0;
	8'd11:sdi<=1'b0;
	8'd13:sdi<=1'b1;
	8'd15:sdi<=1'b0;
	
	8'd17:sdi<=(data[index]>>15);
	8'd19:sdi<=(data[index]>>14);
	8'd21:sdi<=(data[index]>>13);
	8'd23:sdi<=(data[index]>>12);
	8'd25:sdi<=(data[index]>>11);
	8'd27:sdi<=(data[index]>>10);
	8'd29:sdi<=(data[index]>>9);
	8'd31:sdi<=(data[index]>>8);
	8'd33:sdi<=(data[index]>>7);
	8'd35:sdi<=(data[index]>>6);
	8'd37:sdi<=(data[index]>>5);
	8'd39:sdi<=(data[index]>>4);
	8'd41:sdi<=(data[index]>>3);
	8'd43:sdi<=(data[index]>>2);
	8'd45:sdi<=(data[index]>>1);
	8'd47:sdi<=(data[index]>>0);
	default:  sdi<=0;
endcase
end
*/