lcd_283rb06.sim.qmsg

液晶显示驱动源程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 06 12:56:19 2008 " "Info: Processing started: Sun Jul 06 12:56:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off lcd_283rb06 -c lcd_283rb06 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lcd_283rb06 -c lcd_283rb06" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_283rb06.vwf " "Info: Using vector source file \"C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_283rb06.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "lcd_283rb06.vwf lcd_283rb06.sim_ori.vwf " "Info: A backup of lcd_283rb06.vwf called lcd_283rb06.sim_ori.vwf has been created in the db folder" {  } {  } 0 0 "A backup of %1!s! called %2!s! has been created in the db folder" 0 0 "" 0}  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[0\] Input Output " "Warning: Wrong node type for node \"red\[0\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[1\] Input Output " "Warning: Wrong node type for node \"red\[1\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[2\] Input Output " "Warning: Wrong node type for node \"red\[2\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[3\] Input Output " "Warning: Wrong node type for node \"red\[3\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[4\] Input Output " "Warning: Wrong node type for node \"red\[4\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[5\] Input Output " "Warning: Wrong node type for node \"red\[5\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[0\] Input Output " "Warning: Wrong node type for node \"green\[0\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[1\] Input Output " "Warning: Wrong node type for node \"green\[1\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[2\] Input Output " "Warning: Wrong node type for node \"green\[2\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[3\] Input Output " "Warning: Wrong node type for node \"green\[3\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[4\] Input Output " "Warning: Wrong node type for node \"green\[4\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[5\] Input Output " "Warning: Wrong node type for node \"green\[5\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "blue\[0\] Input Output " "Warning: Wrong node type for node \"blue\[0\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "blue\[1\] Input Output " "Warning: Wrong node type for node \"blue\[1\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "blue\[2\] Input Output " "Warning: Wrong node type for node \"blue\[2\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "blue\[3\] Input Output " "Warning: Wrong node type for node \"blue\[3\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "blue\[4\] Input Output " "Warning: Wrong node type for node \"blue\[4\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "blue\[5\] Input Output " "Warning: Wrong node type for node \"blue\[5\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|db18 " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|db18\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|db19 " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|db19\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|db20 " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|db20\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|db21 " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|db21\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|db22 " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|db22\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|db23 " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|db23\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|lcd_283rb06\|penirq " "Warning: Can't find signal in vector source file for input pin \"\|lcd_283rb06\|penirq\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0 "" 0}