lcd_283rb06.fnsim.qmsg

液晶显示驱动源程序代码

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(810) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(810): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 810 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 lcd_init.v(838) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(838): truncated value with size 32 to match size of target (5)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 838 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 lcd_init.v(853) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(853): truncated value with size 32 to match size of target (5)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 853 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(863) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(863): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 863 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(865) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(865): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 865 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 lcd_init.v(1041) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1041): truncated value with size 32 to match size of target (9)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1041 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 lcd_init.v(1169) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1169): truncated value with size 32 to match size of target (9)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1169 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 lcd_init.v(1310) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1310): truncated value with size 32 to match size of target (9)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1310 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[8\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[8\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[7\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[7\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[6\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[6\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[5\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[5\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[4\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[4\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[3\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[3\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[2\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[2\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[1\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[1\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "DataByte2\[0\] 0 lcd_init.v(42) " "Warning (10030): Net \"DataByte2\[0\]\" at lcd_init.v(42) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[0\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[0\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[1\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[1\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[2\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[2\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[3\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[3\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[4\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[4\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[5\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[5\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[6\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[6\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[7\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[7\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataByte1\[8\] lcd_init.v(275) " "Info (10041): Inferred latch for \"DataByte1\[8\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[0\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[0\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[1\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[1\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[2\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[2\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[3\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[3\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[4\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[4\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[5\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[5\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AddressByte\[6\] lcd_init.v(275) " "Info (10041): Inferred latch for \"AddressByte\[6\]\" at lcd_init.v(275)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}