lcd_283rb06.fnsim.qmsg

液晶显示驱动源程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 30 10:17:04 2008 " "Info: Processing started: Mon Jun 30 10:17:04 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_283rb06 -c lcd_283rb06 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_283rb06 -c lcd_283rb06 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "19 lcd_init.v(60) " "Warning (10229): Verilog HDL Expression warning at lcd_init.v(60): truncated literal to match 19 bits" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 60 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(483) " "Warning (10273): Verilog HDL warning at lcd_init.v(483): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 483 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(484) " "Warning (10273): Verilog HDL warning at lcd_init.v(484): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 484 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(485) " "Warning (10273): Verilog HDL warning at lcd_init.v(485): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 485 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(723) " "Warning (10273): Verilog HDL warning at lcd_init.v(723): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 723 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(724) " "Warning (10273): Verilog HDL warning at lcd_init.v(724): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 724 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(725) " "Warning (10273): Verilog HDL warning at lcd_init.v(725): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 725 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd_init.v(476) " "Warning (10268): Verilog HDL information at lcd_init.v(476): Always Construct contains both blocking and non-blocking assignments" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 476 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "START start lcd_init.v(50) " "Info (10281): Verilog HDL Declaration information at lcd_init.v(50): object \"START\" differs only in case from object \"start\" in the same scope" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 50 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "STOP Stop lcd_init.v(52) " "Info (10281): Verilog HDL Declaration information at lcd_init.v(52): object \"STOP\" differs only in case from object \"Stop\" in the same scope" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 52 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_init.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_init.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_283rb06 " "Info: Found entity 1: lcd_283rb06" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_283rb06 " "Info: Elaborating entity \"lcd_283rb06\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "DataByte2 lcd_init.v(42) " "Warning (10858): Verilog HDL warning at lcd_init.v(42): object DataByte2 used but never assigned" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 42 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tempen_sdao lcd_init.v(875) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(875): object \"tempen_sdao\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 875 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tempsda lcd_init.v(877) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(877): object \"tempsda\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 877 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tempscl lcd_init.v(878) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(878): object \"tempscl\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 878 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "main_state lcd_init.v(175) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(175): variable \"main_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 175 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sck_count lcd_init.v(179) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(179): variable \"sck_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 179 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "bit_transfered lcd_init.v(184) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(184): variable \"bit_transfered\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 184 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sck_count lcd_init.v(184) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(184): variable \"sck_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 184 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sck_count lcd_init.v(189) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(189): variable \"sck_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 189 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd_init.v(353) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(353): truncated value with size 32 to match size of target (7)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 353 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "AddressByte lcd_init.v(275) " "Warning (10240): Verilog HDL Always Construct warning at lcd_init.v(275): inferring latch(es) for variable \"AddressByte\", which holds its previous value in one or more paths through the always construct" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "DataByte1 lcd_init.v(275) " "Warning (10240): Verilog HDL Always Construct warning at lcd_init.v(275): inferring latch(es) for variable \"DataByte1\", which holds its previous value in one or more paths through the always construct" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 lcd_init.v(431) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(431): truncated value with size 32 to match size of target (10)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 lcd_init.v(443) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(443): truncated value with size 32 to match size of target (10)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 443 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 lcd_init.v(733) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(733): truncated value with size 32 to match size of target (19)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 733 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(764) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(764): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 764 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(772) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(772): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 772 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(799) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(799): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 799 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}