📄 prev_cmp_lcd_283rb06.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "sw4_out1_reg " "Info: Detected ripple clock \"sw4_out1_reg\" as buffer" { } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1353 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "sw4_out1_reg" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sw1_out1_reg " "Info: Detected ripple clock \"sw1_out1_reg\" as buffer" { } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1310 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "sw1_out1_reg" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "state_dclk\[0\] " "Info: Detected ripple clock \"state_dclk\[0\]\" as buffer" { } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 401 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_dclk\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "rtl~0 " "Info: Detected gated clock \"rtl~0\" as buffer" { } { { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~0" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "state_dclk\[1\] " "Info: Detected ripple clock \"state_dclk\[1\]\" as buffer" { } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 401 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_dclk\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register h_counter\[0\] register red\[2\]~reg0 11.68 MHz 85.616 ns Internal " "Info: Clock \"clock\" has Internal fmax of 11.68 MHz between source register \"h_counter\[0\]\" and destination register \"red\[2\]~reg0\" (period= 85.616 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "36.036 ns + Longest register register " "Info: + Longest register to register delay is 36.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns h_counter\[0\] 1 REG LCFF_X9_Y4_N9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y4_N9; Fanout = 8; REG Node = 'h_counter\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { h_counter[0] } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 461 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.596 ns) 1.052 ns Add8~144 2 COMB LCCOMB_X9_Y4_N8 2 " "Info: 2: + IC(0.456 ns) + CELL(0.596 ns) = 1.052 ns; Loc. = LCCOMB_X9_Y4_N8; Fanout = 2; COMB Node = 'Add8~144'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { h_counter[0] Add8~144 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.138 ns Add8~146 3 COMB LCCOMB_X9_Y4_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.138 ns; Loc. = LCCOMB_X9_Y4_N10; Fanout = 2; COMB Node = 'Add8~146'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add8~144 Add8~146 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.224 ns Add8~148 4 COMB LCCOMB_X9_Y4_N12 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.224 ns; Loc. = LCCOMB_X9_Y4_N12; Fanout = 2; COMB Node = 'Add8~148'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add8~146 Add8~148 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.414 ns Add8~150 5 COMB LCCOMB_X9_Y4_N14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.190 ns) = 1.414 ns; Loc. = LCCOMB_X9_Y4_N14; Fanout = 2; COMB Node = 'Add8~150'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add8~148 Add8~150 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.500 ns Add8~152 6 COMB LCCOMB_X9_Y4_N16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.500 ns; Loc. = LCCOMB_X9_Y4_N16; Fanout = 2; COMB Node = 'Add8~152'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add8~150 Add8~152 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.586 ns Add8~154 7 COMB LCCOMB_X9_Y4_N18 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.586 ns; Loc. = LCCOMB_X9_Y4_N18; Fanout = 2; COMB Node = 'Add8~154'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add8~152 Add8~154 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.672 ns Add8~156 8 COMB LCCOMB_X9_Y4_N20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.672 ns; Loc. = LCCOMB_X9_Y4_N20; Fanout = 2; COMB Node = 'Add8~156'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add8~154 Add8~156 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.758 ns Add8~158 9 COMB LCCOMB_X9_Y4_N22 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.758 ns; Loc. = LCCOMB_X9_Y4_N22; Fanout = 2; COMB Node = 'Add8~158'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add8~156 Add8~158 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.264 ns Add8~159 10 COMB LCCOMB_X9_Y4_N24 4 " "Info: 10: + IC(0.000 ns) + CELL(0.506 ns) = 2.264 ns; Loc. = LCCOMB_X9_Y4_N24; Fanout = 4; COMB Node = 'Add8~159'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add8~158 Add8~159 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.596 ns) 3.562 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~34 11 COMB LCCOMB_X10_Y4_N16 2 " "Info: 11: + IC(0.702 ns) + CELL(0.596 ns) = 3.562 ns; Loc. = LCCOMB_X10_Y4_N16; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~34'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.298 ns" { Add8~159 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~34 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.648 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~36 12 COMB LCCOMB_X10_Y4_N18 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 3.648 ns; Loc. = LCCOMB_X10_Y4_N18; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~34 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~36 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.734 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~38 13 COMB LCCOMB_X10_Y4_N20 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 3.734 ns; Loc. = LCCOMB_X10_Y4_N20; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~38'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~38 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.820 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~40 14 COMB LCCOMB_X10_Y4_N22 1 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 3.820 ns; Loc. = LCCOMB_X10_Y4_N22; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.906 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~42 15 COMB LCCOMB_X10_Y4_N24 1 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 3.906 ns; Loc. = LCCOMB_X10_Y4_N24; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.412 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~43 16 COMB LCCOMB_X10_Y4_N26 10 " "Info: 16: + IC(0.000 ns) + CELL(0.506 ns) = 4.412 ns; Loc. = LCCOMB_X10_Y4_N26; Fanout = 10; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_15~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.370 ns) 5.495 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[115\]~84 17 COMB LCCOMB_X9_Y4_N6 2 " "Info: 17: + IC(0.713 ns) + CELL(0.370 ns) = 5.495 ns; Loc. = LCCOMB_X9_Y4_N6; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[115\]~84'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.083 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[115]~84 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.621 ns) 7.183 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~36 18 COMB LCCOMB_X13_Y4_N4 2 " "Info: 18: + IC(1.067 ns) + CELL(0.621 ns) = 7.183 ns; Loc. = LCCOMB_X13_Y4_N4; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.688 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[115]~84 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~36 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 7.269 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~38 19 COMB LCCOMB_X13_Y4_N6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 7.269 ns; Loc. = LCCOMB_X13_Y4_N6; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~38'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~38 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 7.355 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~40 20 COMB LCCOMB_X13_Y4_N8 1 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 7.355 ns; Loc. = LCCOMB_X13_Y4_N8; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 7.441 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~42 21 COMB LCCOMB_X13_Y4_N10 1 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 7.441 ns; Loc. = LCCOMB_X13_Y4_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 7.947 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~43 22 COMB LCCOMB_X13_Y4_N12 11 " "Info: 22: + IC(0.000 ns) + CELL(0.506 ns) = 7.947 ns; Loc. = LCCOMB_X13_Y4_N12; Fanout = 11; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_16~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.167 ns) + CELL(0.206 ns) 9.320 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[120\]~74 23 COMB LCCOMB_X10_Y4_N4 2 " "Info: 23: + IC(1.167 ns) + CELL(0.206 ns) = 9.320 ns; Loc. = LCCOMB_X10_Y4_N4; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[120\]~74'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[120]~74 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.621 ns) 11.026 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~36 24 COMB LCCOMB_X12_Y4_N4 2 " "Info: 24: + IC(1.085 ns) + CELL(0.621 ns) = 11.026 ns; Loc. = LCCOMB_X12_Y4_N4; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[120]~74 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~36 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 11.112 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~38 25 COMB LCCOMB_X12_Y4_N6 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 11.112 ns; Loc. = LCCOMB_X12_Y4_N6; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~38'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~38 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 11.198 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~40 26 COMB LCCOMB_X12_Y4_N8 1 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 11.198 ns; Loc. = LCCOMB_X12_Y4_N8; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 11.284 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~42 27 COMB LCCOMB_X12_Y4_N10 1 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 11.284 ns; Loc. = LCCOMB_X12_Y4_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 11.790 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~43 28 COMB LCCOMB_X12_Y4_N12 11 " "Info: 28: + IC(0.000 ns) + CELL(0.506 ns) = 11.790 ns; Loc. = LCCOMB_X12_Y4_N12; Fanout = 11; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_17~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.206 ns) 13.074 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[125\]~64 29 COMB LCCOMB_X9_Y4_N2 2 " "Info: 29: + IC(1.078 ns) + CELL(0.206 ns) = 13.074 ns; Loc. = LCCOMB_X9_Y4_N2; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[125\]~64'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[125]~64 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.042 ns) + CELL(0.596 ns) 14.712 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~36 30 COMB LCCOMB_X12_Y4_N22 2 " "Info: 30: + IC(1.042 ns) + CELL(0.596 ns) = 14.712 ns; Loc. = LCCOMB_X12_Y4_N22; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.638 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[125]~64 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~36 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 14.798 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~38 31 COMB LCCOMB_X12_Y4_N24 2 " "Info: 31: + IC(0.000 ns) + CELL(0.086 ns) = 14.798 ns; Loc. = LCCOMB_X12_Y4_N24; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~38'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~38 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 14.884 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~40 32 COMB LCCOMB_X12_Y4_N26 1 " "Info: 32: + IC(0.000 ns) + CELL(0.086 ns) = 14.884 ns; Loc. = LCCOMB_X12_Y4_N26; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 14.970 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~42 33 COMB LCCOMB_X12_Y4_N28 1 " "Info: 33: + IC(0.000 ns) + CELL(0.086 ns) = 14.970 ns; Loc. = LCCOMB_X12_Y4_N28; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 15.476 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~43 34 COMB LCCOMB_X12_Y4_N30 11 " "Info: 34: + IC(0.000 ns) + CELL(0.506 ns) = 15.476 ns; Loc. = LCCOMB_X12_Y4_N30; Fanout = 11; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_18~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.370 ns) 16.518 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[130\]~59 35 COMB LCCOMB_X13_Y4_N26 2 " "Info: 35: + IC(0.672 ns) + CELL(0.370 ns) = 16.518 ns; Loc. = LCCOMB_X13_Y4_N26; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[130\]~59'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.042 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[130]~59 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.596 ns) 18.203 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~36 36 COMB LCCOMB_X12_Y3_N4 2 " "Info: 36: + IC(1.089 ns) + CELL(0.596 ns) = 18.203 ns; Loc. = LCCOMB_X12_Y3_N4; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.685 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[130]~59 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~36 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 18.289 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~38 37 COMB LCCOMB_X12_Y3_N6 2 " "Info: 37: + IC(0.000 ns) + CELL(0.086 ns) = 18.289 ns; Loc. = LCCOMB_X12_Y3_N6; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~38'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~38 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 18.375 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~40 38 COMB LCCOMB_X12_Y3_N8 1 " "Info: 38: + IC(0.000 ns) + CELL(0.086 ns) = 18.375 ns; Loc. = LCCOMB_X12_Y3_N8; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 18.461 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~42 39 COMB LCCOMB_X12_Y3_N10 1 " "Info: 39: + IC(0.000 ns) + CELL(0.086 ns) = 18.461 ns; Loc. = LCCOMB_X12_Y3_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 18.967 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~43 40 COMB LCCOMB_X12_Y3_N12 11 " "Info: 40: + IC(0.000 ns) + CELL(0.506 ns) = 18.967 ns; Loc. = LCCOMB_X12_Y3_N12; Fanout = 11; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_19~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.206 ns) 20.302 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[137\]~2071 41 COMB LCCOMB_X13_Y4_N18 3 " "Info: 41: + IC(1.129 ns) + CELL(0.206 ns) = 20.302 ns; Loc. = LCCOMB_X13_Y4_N18; Fanout = 3; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[137\]~2071'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[137]~2071 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.275 ns) + CELL(0.621 ns) 22.198 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_20~40 42 COMB LCCOMB_X14_Y3_N24 1 " "Info: 42: + IC(1.275 ns) + CELL(0.621 ns) = 22.198 ns; Loc. = LCCOMB_X14_Y3_N24; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_20~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.896 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[137]~2071 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 22.284 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_20~42 43 COMB LCCOMB_X14_Y3_N26 1 " "Info: 43: + IC(0.000 ns) + CELL(0.086 ns) = 22.284 ns; Loc. = LCCOMB_X14_Y3_N26; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_20~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 22.790 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_20~43 44 COMB LCCOMB_X14_Y3_N28 14 " "Info: 44: + IC(0.000 ns) + CELL(0.506 ns) = 22.790 ns; Loc. = LCCOMB_X14_Y3_N28; Fanout = 14; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_20~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.355 ns) + CELL(0.366 ns) 24.511 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[143\]~2072 45 COMB LCCOMB_X13_Y4_N16 1 " "Info: 45: + IC(1.355 ns) + CELL(0.366 ns) = 24.511 ns; Loc. = LCCOMB_X13_Y4_N16; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[143\]~2072'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.721 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[143]~2072 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.621 ns) 25.859 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_21~42 46 COMB LCCOMB_X13_Y3_N26 1 " "Info: 46: + IC(0.727 ns) + CELL(0.621 ns) = 25.859 ns; Loc. = LCCOMB_X13_Y3_N26; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_21~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.348 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[143]~2072 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 26.365 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_21~43 47 COMB LCCOMB_X13_Y3_N28 14 " "Info: 47: + IC(0.000 ns) + CELL(0.506 ns) = 26.365 ns; Loc. = LCCOMB_X13_Y3_N28; Fanout = 14; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_21~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.206 ns) 27.321 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[148\]~2074 48 COMB LCCOMB_X12_Y3_N28 1 " "Info: 48: + IC(0.750 ns) + CELL(0.206 ns) = 27.321 ns; Loc. = LCCOMB_X12_Y3_N28; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[148\]~2074'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.956 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[148]~2074 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.621 ns) 29.009 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_23~42 49 COMB LCCOMB_X13_Y3_N10 1 " "Info: 49: + IC(1.067 ns) + CELL(0.621 ns) = 29.009 ns; Loc. = LCCOMB_X13_Y3_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_23~42'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.688 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[148]~2074 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~42 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 29.515 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_23~43 50 COMB LCCOMB_X13_Y3_N12 10 " "Info: 50: + IC(0.000 ns) + CELL(0.506 ns) = 29.515 ns; Loc. = LCCOMB_X13_Y3_N12; Fanout = 10; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_23~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.370 ns) 31.336 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[151\]~18 51 COMB LCCOMB_X14_Y7_N18 1 " "Info: 51: + IC(1.451 ns) + CELL(0.370 ns) = 31.336 ns; Loc. = LCCOMB_X14_Y7_N18; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|StageOut\[151\]~18'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.821 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[151]~18 } "NODE_NAME" } } { "db/alt_u_div_i2f.tdf" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/db/alt_u_div_i2f.tdf" 199 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.596 ns) 33.102 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~36 52 COMB LCCOMB_X14_Y4_N10 1 " "Info: 52: + IC(1.170 ns) + CELL(0.596 ns) = 33.102 ns; Loc. = LCCOMB_X14_Y4_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.766 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[151]~18 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~36 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 33.188 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~38 53 COMB LCCOMB_X14_Y4_N12 1 " "Info: 53: + IC(0.000 ns) + CELL(0.086 ns) = 33.188 ns; Loc. = LCCOMB_X14_Y4_N12; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~38'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~38 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 33.378 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~40 54 COMB LCCOMB_X14_Y4_N14 1 " "Info: 54: + IC(0.000 ns) + CELL(0.190 ns) = 33.378 ns; Loc. = LCCOMB_X14_Y4_N14; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~40'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~40 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 33.884 ns lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~41 55 COMB LCCOMB_X14_Y4_N16 3 " "Info: 55: + IC(0.000 ns) + CELL(0.506 ns) = 33.884 ns; Loc. = LCCOMB_X14_Y4_N16; Fanout = 3; COMB Node = 'lpm_divide:Div0\|lpm_divide_eem:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|op_24~41'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~41 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.370 ns) 34.643 ns Selector35~71 56 COMB LCCOMB_X14_Y4_N30 1 " "Info: 56: + IC(0.389 ns) + CELL(0.370 ns) = 34.643 ns; Loc. = LCCOMB_X14_Y4_N30; Fanout = 1; COMB Node = 'Selector35~71'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.759 ns" { lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~41 Selector35~71 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 550 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 35.214 ns Selector35~72 57 COMB LCCOMB_X14_Y4_N4 1 " "Info: 57: + IC(0.365 ns) + CELL(0.206 ns) = 35.214 ns; Loc. = LCCOMB_X14_Y4_N4; Fanout = 1; COMB Node = 'Selector35~72'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { Selector35~71 Selector35~72 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 550 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.460 ns) 36.036 ns red\[2\]~reg0 58 REG LCFF_X14_Y4_N1 1 " "Info: 58: + IC(0.362 ns) + CELL(0.460 ns) = 36.036 ns; Loc. = LCFF_X14_Y4_N1; Fanout = 1; REG Node = 'red\[2\]~reg0'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { Selector35~72 red[2]~reg0 } "NODE_NAME" } } { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1234 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.925 ns ( 46.97 % ) " "Info: Total cell delay = 16.925 ns ( 46.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "19.111 ns ( 53.03 % ) " "Info: Total interconnect delay = 19.111 ns ( 53.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "36.036 ns" { h_counter[0] Add8~144 Add8~146 Add8~148 Add8~150 Add8~152 Add8~154 Add8~156 Add8~158 Add8~159 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~34 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[115]~84 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[120]~74 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[125]~64 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[130]~59 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[137]~2071 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[143]~2072 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[148]~2074 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[151]~18 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~41 Selector35~71 Selector35~72 red[2]~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "36.036 ns" { h_counter[0] Add8~144 Add8~146 Add8~148 Add8~150 Add8~152 Add8~154 Add8~156 Add8~158 Add8~159 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~34 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_15~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[115]~84 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_16~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[120]~74 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_17~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[125]~64 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_18~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[130]~59 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_19~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[137]~2071 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_20~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[143]~2072 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_21~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[148]~2074 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~42 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_23~43 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|StageOut[151]~18 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~36 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~38 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~40 lpm_divide:Div0|lpm_divide_eem:auto_generated|sign_div_unsign_olh:divider|alt_u_div_i2f:divider|op_24~41 Selector35~71 Selector35~72 red[2]~reg0 } { 0.000ns 0.456ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.702ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.713ns 1.067ns 0.000ns 0.000ns 0.000ns 0.000ns 1.167ns 1.085ns 0.000ns 0.000ns 0.000ns 0.000ns 1.078ns 1.042ns 0.000ns 0.000ns 0.000ns 0.000ns 0.672ns 1.089ns 0.000ns 0.000ns 0.000ns 0.000ns 1.129ns 1.275ns 0.000ns 0.000ns 1.355ns 0.727ns 0.000ns 0.750ns 1.067ns 0.000ns 1.451ns 1.170ns 0.000ns 0.000ns 0.000ns 0.389ns 0.365ns 0.362ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.621ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.621ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.596ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.596ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.621ns 0.086ns 0.506ns 0.366ns 0.621ns 0.506ns 0.206ns 0.621ns 0.506ns 0.370ns 0.596ns 0.086ns 0.190ns 0.506ns 0.370ns 0.206ns 0.460ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.508 ns - Smallest " "Info: - Smallest clock skew is -6.508 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.736 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clock 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(⌨️ 快捷键说明
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