seg70.fit.summary

来自「CPLD VHDL CODE非常好的参考资料」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Tue Nov 22 22:13:33 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : seg70
Top-level Entity Name : seg70
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 32 / 128 ( 25 % )
Total pins : 22 / 68 ( 32 % )