📄 i2c.fit.rpt
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+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 28.63) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 3 ; 0 ;
; 4 - 7 ; 0 ;
; 8 - 11 ; 0 ;
; 12 - 15 ; 0 ;
; 16 - 19 ; 0 ;
; 20 - 23 ; 1 ;
; 24 - 27 ; 4 ;
; 28 - 31 ; 0 ;
; 32 - 35 ; 2 ;
; 36 - 39 ; 1 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 15.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 2 ;
; 16 ; 6 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 17 ;
; 2 ; 8 ;
; 3 ; 1 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 3.00) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+-------------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC2 ; clk, rst, cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[11], cnt_delay[10], cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[15], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state[1], Mux~17930, reduce_nor~56sexp, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13], reduce_nor~58 ;
; A ; LC13 ; main_state[0], i2c_state[2], inner_state[0], i2c_state[0], phase3, sda_buf, phase1, wr_input, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[13], cnt_delay[12], main_state[1] ; Mux~17936 ;
; A ; LC6 ; clk, rst, cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[10], start_delaycnt, reduce_nor~56sexp, cnt_delay[18], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[13], cnt_delay[12] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state[1], Mux~17930, reduce_nor~56sexp, cnt_delay[8], reduce_nor~58 ;
; A ; LC14 ; Mux~17930, main_state[0], i2c_state[1], phase1, i2c_state[2], sda_buf, inner_state[0], inner_state[3], inner_state[1] ; main_state[0] ;
; A ; LC10 ; clk, rst, rd_input, wr_input, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[13], cnt_delay[12], main_state[0], main_state[1], phase1, sda_buf, i2c_state[2], i2c_state[1], inner_state[0], inner_state[3], inner_state[1], inner_state[2], i2c_state[0], phase3 ; writeData_reg[3], writeData_reg[1], writeData_reg[2], writeData_reg[0], i2c_state[1], inner_state[2], inner_state[1], Mux~17742, Mux~17743, Mux~17755, inner_state[0], inner_state[3], i2c_state[0], i2c_state[2], readData_reg[0], readData_reg[1], readData_reg[2], sda_buf, readData_reg[3], readData_reg[4], readData_reg[5], readData_reg[6], start_delaycnt, readData_reg[7], main_state[1], scl_xhdl1, rtl~1333, Mux~17849, Mux~17854, Mux~17860, Mux~17863, Mux~17873, rtl~1337, sda~14, readData_reg[0]~297, readData_reg[1]~301, readData_reg[2]~305, readData_reg[3]~309, readData_reg[4]~313, Mux~17930, readData_reg[5]~317, readData_reg[6]~321, Mux~17942 ;
; A ; LC1 ; clk, rst, cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[8], start_delaycnt, reduce_nor~56sexp, cnt_delay[18], cnt_delay[10], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[13], cnt_delay[12] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state[1], Mux~17930, reduce_nor~56sexp, reduce_nor~58 ;
; A ; LC5 ; clk, rst, rtl~1337, i2c_state[0], inner_state[1], inner_state[2], inner_state[0], phase3, i2c_state[1], main_state[0], main_state[1], inner_state[3], i2c_state[2] ; i2c_state[1], inner_state[2], inner_state[1], Mux~17742, Mux~17743, inner_state[0], inner_state[3], i2c_state[0], i2c_state[2], readData_reg[0], readData_reg[1], readData_reg[2], Mux~17780, Mux~17786, Mux~17790, Mux~17795, Mux~17798, Mux~17817, Mux~17823, readData_reg[3], readData_reg[4], readData_reg[5], main_state[0], readData_reg[6], readData_reg[7], main_state[1], rtl~1331, rtl~1333, Mux~17849, Mux~17854, Mux~17860, Mux~17863, Mux~17869, rtl~1337, sda~14, readData_reg[0]~297, readData_reg[1]~301, Mux~17879, Mux~17881, Mux~17887, Mux~17893, Mux~17902, Mux~17907, Mux~17913, Mux~17919, Mux~17924, readData_reg[2]~305, readData_reg[3]~309, readData_reg[4]~313, Mux~17936, readData_reg[5]~317, readData_reg[6]~321 ;
; A ; LC7 ; clk, rst, main_state[1], i2c_state[1], inner_state[3], inner_state[1], inner_state[2], inner_state[0], main_state[0], phase3, i2c_state[2], i2c_state[0] ; i2c_state[1], inner_state[2], inner_state[1], Mux~17742, Mux~17743, Mux~17753, Mux~17754, Mux~17755, inner_state[0], inner_state[3], i2c_state[0], i2c_state[2], readData_reg[0], readData_reg[1], readData_reg[2], Mux~17780, Mux~17790, Mux~17805, Mux~17808, Mux~17817, Mux~17823, readData_reg[3], readData_reg[4], readData_reg[5], main_state[0], readData_reg[6], readData_reg[7], main_state[1], rtl~1333, Mux~17849, Mux~17854, Mux~17860, Mux~17863, Mux~17869, Mux~17873, rtl~1337, sda~14, readData_reg[0]~297, readData_reg[1]~301, Mux~17879, Mux~17881, Mux~17887, Mux~17902, Mux~17907, Mux~17913, Mux~17919, readData_reg[2]~305, readData_reg[3]~309, readData_reg[4]~313, Mux~17930, readData_reg[5]~317, readData_reg[6]~321 ;
; A ; LC16 ; clk, rst, cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[3], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[3], cnt_delay[4], cnt_delay[5], cnt_delay[6], cnt_delay[7], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state[1], Mux~17930, reduce_nor~56sexp, reduce_nor~58 ;
; A ; LC12 ; clk, rst, cnt_delay[1], cnt_delay[0], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[1], cnt_delay[2], cnt_delay[3], cnt_delay[4], cnt_delay[5], cnt_delay[6], cnt_delay[7], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state[1], Mux~17930, reduce_nor~56sexp, reduce_nor~58 ;
; A ; LC4 ; inner_state[1], inner_state[2], inner_state[0], phase3, i2c_state[1], i2c_state[2], main_state[0], main_state[1], inner_state[3], i2c_state[0] ; inner_state[3] ;
; A ; LC8 ; clk, rst, cnt_delay[18], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[10], cnt_delay[11], cnt_delay[8], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[19], start_delaycnt, reduce_nor~56sexp ; cnt_delay[19], start_delaycnt, cnt_delay[0], main_state[1], Mux~17930, reduce_nor~56sexp, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13], cnt_delay[18], reduce_nor~58 ;
; A ; LC15 ; clk, rst, Mux~17936, main_state[0], i2c_state[1], i2c_state[2], inner_state[2], inner_state[3], i2c_state[0], inner_state[0], inner_state[1] ; writeData_reg[3], writeData_reg[1], writeData_reg[2], writeData_reg[0], i2c_state[1], inner_state[2], inner_state[1], Mux~17742, Mux~17743, inner_state[3], i2c_state[0], i2c_state[2], readData_reg[0], readData_reg[1], readData_reg[2], sda_buf, readData_reg[3], readData_reg[4], readData_reg[5], main_state[0], readData_reg[6], start_delaycnt, readData_reg[7], main_state[1], scl_xhdl1, rtl~1331, rtl~1333, Mux~17849, Mux~17854, Mux~17860, Mux~17863, Mux~17869, Mux~17873, rtl~1337, sda~14, readData_reg[0]~297, readData_reg[1]~301, readData_reg[2]~305, readData_reg[3]~309, readData_reg[4]~313, Mux~17930, Mux~17936, readData_reg[5]~317, readData_reg[6]~321, Mux~17942 ;
; A ; LC3 ; clk, rst, rd_input, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[13], cnt_delay[12], start_delaycnt, wr_input, main_state[1], main_state[0] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[1], cnt_delay[2], cnt_delay[3], cnt_delay[4], cnt_delay[5], cnt_delay[6], cnt_delay[7], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18] ;
; A ; LC11 ; clk, rst, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[13], cnt_delay[12], cnt_delay[0], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[1], cnt_delay[2], cnt_delay[3], cnt_delay[4], cnt_delay[5], cnt_delay[6], cnt_delay[7], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state[1], Mux~17930, reduce_nor~56sexp, reduce_nor~58 ;
; B ; LC22 ; Mux~17907, inner_state[0], i2c_state[1], inner_state[3], i2c_state[0], inner_state[2], inner_state[1], phase1, sda_buf, phase0, phase3, Mux~17806, sda ; Mux~17817 ;
; B ; LC23 ; Mux~17913, Mux~17947, i2c_state[1], sda_buf, phase3, Mux~17809, inner_state[0], inner_state[3], Mux~17810, i2c_state[0], inner_state[2], Mux~17811, Mux~17808 ; sda_buf ;
; B ; LC25 ; clk, rst, clk_div[7], lpm_counter:cnt_scan_rtl_0|dffs[0], clk_div[5], clk_div[4], clk_div[3], clk_div[2], clk_div[6], clk_div[1] ; clk_div[2], clk_div[5], clk_div[7], clk_div[6], phase0, phase1, phase2, phase3 ;
; B ; LC30 ; clk, rst, phase0, lpm_counter:cnt_scan_rtl_0|dffs[0], clk_div[5], clk_div[3], clk_div[7], clk_div[2], clk_div[6], clk_div[4], clk_div[1] ; phase0, Mux~17780, Mux~17786, Mux~17798, Mux~17809, Mux~17811, Mux~17823, scl_xhdl1, Mux~17893, Mux~17907, Mux~17913, Mux~17924 ;
; B ; LC27 ; clk, rst, phase1, clk_div[6], clk⌨️ 快捷键说明
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