i2c.fit.eqn

CPLD VHDL CODE非常好的参考资料

cnt_delay[18] = TFFE(cnt_delay[18]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--main_state[1] is main_state[1] at LC10
main_state[1]_p1_out = !rd_input & wr_input & cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[12] & !main_state[0] & !main_state[1];
main_state[1]_p2_out = !main_state[0] & main_state[1] & phase1 & sda_buf & !i2c_state[2] & !i2c_state[1] & inner_state[0] & inner_state[3] & !inner_state[1] & !inner_state[2];
main_state[1]_p3_out = !main_state[0] & main_state[1] & phase1 & sda_buf & !i2c_state[1] & inner_state[0] & inner_state[3] & !inner_state[1] & !inner_state[2] & !i2c_state[0];
main_state[1]_p4_out = !main_state[0] & main_state[1] & !i2c_state[2] & i2c_state[1] & !inner_state[0] & inner_state[3] & inner_state[1] & !inner_state[2] & i2c_state[0] & phase3;
main_state[1]_or_out = main_state[1]_p1_out # main_state[1]_p2_out # main_state[1]_p3_out # main_state[1]_p4_out;
main_state[1]_reg_input = main_state[1]_or_out;
main_state[1] = TFFE(main_state[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--scl_xhdl1 is scl_xhdl1 at LC40
scl_xhdl1_p0_out = scl_xhdl1 & !phase2;
scl_xhdl1_p1_out = phase0 & !main_state[0];
scl_xhdl1_p2_out = phase0 & !main_state[1];
scl_xhdl1_p3_out = main_state[0] & main_state[1] & scl_xhdl1;
scl_xhdl1_or_out = A1L39 # scl_xhdl1_p0_out # scl_xhdl1_p1_out # scl_xhdl1_p2_out # scl_xhdl1_p3_out;
scl_xhdl1_reg_input = scl_xhdl1_or_out;
scl_xhdl1 = DFFE(scl_xhdl1_reg_input, GLOBAL(clk), , rst, );


--A1L541 is rtl~1331 at LC65
A1L541_p1_out = !i2c_state[1] & inner_state[1] & !inner_state[3] & inner_state[0] & phase3 & !i2c_state[2] & !main_state[0] & inner_state[2];
A1L541 = A1L541_p1_out;


--A1L641 is rtl~1333 at LC18
A1L641_p1_out = !main_state[0] & !i2c_state[1] & !inner_state[3] & inner_state[0] & phase3 & !i2c_state[2] & inner_state[1];
A1L641_p2_out = main_state[0] & !i2c_state[1] & !inner_state[3] & inner_state[0] & phase3 & !i2c_state[2] & !main_state[1];
A1L641_p3_out = main_state[0] & !inner_state[3] & inner_state[0] & phase3 & !i2c_state[2] & !main_state[1] & !i2c_state[0];
A1L641 = A1L641_p1_out # A1L641_p2_out # A1L641_p3_out;


--A1L57 is Mux~17849 at LC42
A1L57_p1_out = link & main_state[1] & !main_state[0] & inner_state[1];
A1L57_p2_out = main_state[1] & !main_state[0] & inner_state[1] & !i2c_state[2] & phase3 & !inner_state[3] & !i2c_state[1];
A1L57_p3_out = main_state[1] & !main_state[0] & inner_state[1] & phase3 & !inner_state[3] & !i2c_state[1] & !i2c_state[0];
A1L57_p4_out = link & main_state[1] & !main_state[0] & inner_state[2];
A1L57 = A1L57_p1_out # A1L57_p2_out # A1L57_p3_out # A1L57_p4_out;


--A1L67 is Mux~17854 at LC43
A1L67_p0_out = main_state[1] & !main_state[0] & !inner_state[3] & link;
A1L67_p1_out = !i2c_state[2] & phase3 & main_state[1] & !main_state[0] & inner_state[2] & !inner_state[3] & !i2c_state[1];
A1L67_p2_out = phase3 & main_state[1] & !main_state[0] & inner_state[2] & !inner_state[3] & !i2c_state[1] & !i2c_state[0];
A1L67_p3_out = !i2c_state[2] & phase3 & main_state[1] & !main_state[0] & !inner_state[2] & !i2c_state[1] & inner_state[0] & !inner_state[1];
A1L67_p4_out = !i2c_state[2] & phase3 & main_state[1] & !main_state[0] & !inner_state[2] & inner_state[3] & i2c_state[0] & inner_state[0] & !inner_state[1];
A1L67 = A1L57 # A1L67_p0_out # A1L67_p1_out # A1L67_p2_out # A1L67_p3_out # A1L67_p4_out;


--A1L77 is Mux~17860 at LC52
A1L77_p1_out = phase1 & main_state[0] & !i2c_state[1] & !inner_state[2] & !inner_state[1] & !inner_state[0] & !inner_state[3] & !i2c_state[0] & !main_state[1] & !i2c_state[2] & !link;
A1L77_p2_out = main_state[0] & !i2c_state[1] & !inner_state[2] & !inner_state[1] & inner_state[0] & !main_state[1] & !i2c_state[2] & !link & phase3;
A1L77 = A1L77_p1_out # A1L77_p2_out;


--A1L87 is Mux~17863 at LC53
A1L87_p0_out = main_state[0] & phase3 & inner_state[2] & !i2c_state[0] & !main_state[1] & !i2c_state[2] & !link & !inner_state[3];
A1L87_p1_out = !phase1 & main_state[0] & phase3 & !inner_state[2] & !inner_state[1] & inner_state[0] & !i2c_state[0] & !main_state[1] & !i2c_state[2] & !link;
A1L87_p2_out = main_state[0] & phase3 & inner_state[1] & !main_state[1] & !i2c_state[2] & !link & !i2c_state[1] & !inner_state[3];
A1L87_p3_out = main_state[0] & phase3 & inner_state[1] & !i2c_state[0] & !main_state[1] & !i2c_state[2] & !link & !inner_state[3];
A1L87_p4_out = main_state[0] & phase3 & inner_state[2] & !main_state[1] & !i2c_state[2] & !link & !i2c_state[1] & !inner_state[3];
A1L87 = A1L77 # A1L87_p0_out # A1L87_p1_out # A1L87_p2_out # A1L87_p3_out # A1L87_p4_out;


--A1L97 is Mux~17869 at LC49
A1L97_p1_out = phase3 & !i2c_state[2] & !inner_state[3] & inner_state[0] & !main_state[0] & i2c_state[0];
A1L97_p2_out = phase3 & !inner_state[3] & inner_state[0] & !main_state[0] & !i2c_state[0] & !i2c_state[1];
A1L97_p3_out = phase3 & !i2c_state[2] & inner_state[0] & !main_state[0] & i2c_state[0] & !inner_state[2] & !inner_state[1];
A1L97 = A1L97_p1_out # A1L97_p2_out # A1L97_p3_out;


--A1L08 is Mux~17873 at LC50
A1L08_p0_out = main_state[0] & main_state[1] & !inner_state[0];
A1L08_p1_out = !main_state[0] & !main_state[1];
A1L08_p2_out = !main_state[1] & i2c_state[1] & phase3 & !i2c_state[2] & inner_state[0] & !i2c_state[0] & !inner_state[2] & !inner_state[1] & !phase1;
A1L08_p3_out = !phase3 & !inner_state[0];
A1L08_p4_out = main_state[1] & i2c_state[1] & !inner_state[0] & !i2c_state[0];
A1L08 = A1L97 # A1L08_p0_out # A1L08_p1_out # A1L08_p2_out # A1L08_p3_out # A1L08_p4_out;


--A1L741 is rtl~1337 at LC4
A1L741_p1_out = inner_state[1] & inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & !i2c_state[2] & main_state[0] & !main_state[1] & !inner_state[3];
A1L741_p2_out = inner_state[1] & inner_state[2] & inner_state[0] & phase3 & !i2c_state[2] & main_state[0] & !main_state[1] & !inner_state[3] & !i2c_state[0];
A1L741_p3_out = inner_state[1] & inner_state[2] & inner_state[0] & phase3 & !i2c_state[2] & !main_state[0] & main_state[1] & !inner_state[3] & i2c_state[0];
A1L741 = A1L741_p1_out # A1L741_p2_out # A1L741_p3_out;


--A1L351 is sda~14 at LC60
A1L351_p1_out = A1L251 & phase1 & i2c_state[1] & !inner_state[0] & !inner_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[0];
A1L351_p2_out = A1L251 & phase1 & i2c_state[1] & inner_state[0] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[0];
A1L351_p3_out = A1L251 & phase1 & i2c_state[1] & inner_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[0];
A1L351 = A1L351_p1_out # A1L351_p2_out # A1L351_p3_out;


--A1L201 is readData_reg[0]~297 at LC103
A1L201_p1_out = readData_reg[0] & phase1 & i2c_state[1] & !inner_state[0] & !inner_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[1];
A1L201_p2_out = readData_reg[0] & phase1 & i2c_state[1] & inner_state[0] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[1];
A1L201_p3_out = readData_reg[0] & phase1 & i2c_state[1] & inner_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[1];
A1L201 = A1L201_p1_out # A1L201_p2_out # A1L201_p3_out;


--A1L401 is readData_reg[1]~301 at LC69
A1L401_p1_out = readData_reg[1] & phase1 & i2c_state[1] & !inner_state[0] & !inner_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[2];
A1L401_p2_out = readData_reg[1] & phase1 & i2c_state[1] & inner_state[0] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[2];
A1L401_p3_out = readData_reg[1] & phase1 & i2c_state[1] & inner_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[2];
A1L401 = A1L401_p1_out # A1L401_p2_out # A1L401_p3_out;


--A1L18 is Mux~17879 at LC62
A1L18_p1_out = sda_buf & inner_state[1] & !i2c_state[1] & !i2c_state[0] & inner_state[3];
A1L18 = A1L18_p1_out;


--A1L28 is Mux~17881 at LC63
A1L28_p0_out = sda_buf & !i2c_state[1] & !i2c_state[0] & !inner_state[2] & !inner_state[0] & !phase1;
A1L28_p1_out = sda_buf & inner_state[1] & !i2c_state[1] & !i2c_state[0] & !phase3;
A1L28_p2_out = sda_buf & !i2c_state[1] & !i2c_state[0] & inner_state[3] & inner_state[2];
A1L28_p3_out = sda_buf & !i2c_state[1] & !i2c_state[0] & !phase3 & inner_state[2];
A1L28_p4_out = sda_buf & !i2c_state[1] & !i2c_state[0] & inner_state[3] & !inner_state[0];
A1L28 = A1L18 # A1L28_p0_out # A1L28_p1_out # A1L28_p2_out # A1L28_p3_out # A1L28_p4_out;


--A1L38 is Mux~17887 at LC57
A1L38_p0_out = i2c_state[1] & phase3 & inner_state[1] & inner_state[2] & !inner_state[3] & inner_state[0] & !writeData_reg[0];
A1L38_p1_out = i2c_state[0] & i2c_state[1];
A1L38_p2_out = i2c_state[1] & writeData_reg[3] & phase3 & !inner_state[1] & inner_state[2] & !inner_state[3] & !inner_state[0];
A1L38_p3_out = i2c_state[1] & phase3 & inner_state[1] & inner_state[2] & !inner_state[3] & !inner_state[0] & writeData_reg[1];
A1L38_p4_out = i2c_state[1] & phase3 & !inner_state[1] & inner_state[2] & !inner_state[3] & inner_state[0] & !writeData_reg[2];
A1L38 = A1L38_p0_out # A1L38_p1_out # A1L38_p2_out # A1L38_p3_out # A1L38_p4_out;


--A1L48 is Mux~17893 at LC58
A1L48_p0_out = !inner_state[1] & !inner_state[2] & i2c_state[1] & inner_state[0] & inner_state[3] & A1L251 & phase0 & phase1;
A1L48_p1_out = !inner_state[1] & !inner_state[2] & i2c_state[1] & sda_buf & !inner_state[0];
A1L48_p2_out = i2c_state[1] & sda_buf & !phase3 & !inner_state[3];
A1L48_p3_out = !inner_state[1] & !inner_state[2] & i2c_state[1] & inner_state[0] & !phase3 & inner_state[3] & A1L251 & phase0;
A1L48_p4_out = i2c_state[1] & sda_buf & !phase3 & !phase0;
A1L48 = A1L38 # A1L48_p0_out # A1L48_p1_out # A1L48_p2_out # A1L48_p3_out # A1L48_p4_out;


--A1L58 is Mux~17899 at LC55
A1L58_p1_out = sda_buf & i2c_state[2];
A1L58_p2_out = sda_buf & A1L26;
A1L58 = A1L58_p1_out # A1L58_p2_out;


--A1L68 is Mux~17902 at LC20
A1L68_p1_out = !inner_state[0] & i2c_state[1] & sda_buf & A1L251;
A1L68_p2_out = inner_state[0] & !i2c_state[1] & sda_buf & !inner_state[3] & !phase3;
A1L68_p3_out = !inner_state[0] & sda_buf & A1L251 & i2c_state[0] & !inner_state[1];
A1L68_p4_out = !inner_state[0] & sda_buf & !inner_state[3] & i2c_state[0] & !inner_state[1] & !inner_state[2];
A1L68 = A1L68_p1_out # A1L68_p2_out # A1L68_p3_out # A1L68_p4_out;


--A1L78 is Mux~17907 at LC21
A1L78_p0_out = !inner_state[0] & i2c_state[1] & inner_state[3] & i2c_state[0] & !inner_state[2] & !inner_state[1] & A1L251 & phase0;
A1L78_p1_out = inner_state[0] & !i2c_state[1] & inner_state[3] & i2c_state[0] & !inner_state[2] & phase3 & !inner_state[1];
A1L78_p2_out = !inner_state[0] & !i2c_state[1] & !inner_state[3] & i2c_state[0] & inner_state[2] & phase3;
A1L78_p3_out = !inner_state[0] & !i2c_state[0] & !inner_state[2] & sda_buf & !phase1;
A1L78_p4_out = inner_state[0] & !i2c_state[1] & inner_state[3] & !inner_state[2] & !phase3 & !inner_state[1] & A1L251 & phase0;
A1L78 = A1L68 # A1L78_p0_out # A1L78_p1_out # A1L78_p2_out # A1L78_p3_out # A1L78_p4_out;


--A1L88 is Mux~17913 at LC22
A1L88_p0_out = i2c_state[1] & !inner_state[3] & i2c_state[0] & phase0 & A1L86 & A1L251;
A1L88_p1_out = !inner_state[0] & i2c_state[1] & inner_state[3] & i2c_state[0] & !inner_state[2] & inner_state[1] & phase1;
A1L88_p2_out = i2c_state[1] & !i2c_state[0] & sda_buf;
A1L88_p3_out = i2c_state[1] & !inner_state[3] & sda_buf & !phase0;
A1L88_p4_out = inner_state[0] & i2c_state[1] & inner_state[3] & sda_buf & !phase3;
A1L88 = A1L78 # A1L88_p0_out # A1L88_p1_out # A1L88_p2_out # A1L88_p3_out # A1L88_p4_out;


--A1L98 is Mux~17919 at LC34
A1L98_p1_out = sda_buf & i2c_state[1];
A1L98_p2_out = sda_buf & i2c_state[0];
A1L98_p3_out = sda_buf & !inner_state[3] & !phase3 & inner_state[0];
A1L98_p4_out = sda_buf & !inner_state[0] & !phase1 & !inner_state[2];
A1L98 = A1L98_p1_out # A1L98_p2_out # A1L98_p3_out # A1L98_p4_out;


--A1L09 is Mux~17924 at LC35
A1L09_p0_out = sda_buf & inner_state[3] & !phase0;
A1L09_p1_out = sda_buf & inner_state[1] & inner_state[3];
A1L09_p2_out = sda_buf & inner_state[1] & !phase3;
A1L09_p3_out = sda_buf & inner_state[3] & inner_state[2];
A1L09_p4_out = sda_buf & !phase3 & inner_state[2];
A1L09 = A1L98 # A1L09_p0_out # A1L09_p1_out # A1L09_p2_out # A1L09_p3_out # A1L09_p4_out;


--A1L601 is readData_reg[2]~305 at LC67
A1L601_p1_out = readData_reg[2] & phase1 & i2c_state[1] & !inner_state[0] & !inner_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[3];
A1L601_p2_out = readData_reg[2] & phase1 & i2c_state[1] & inner_state[0] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[3];
A1L601_p3_out = readData_reg[2] & phase1 & i2c_state[1] & inner_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[3];
A1L601 = A1L601_p1_out # A1L601_p2_out # A1L601_p3_ou