i2c.fit.eqn

CPLD VHDL CODE非常好的参考资料

--A1L56 is Mux~17795 at LC95
A1L56_p1_out = inner_state[3] & inner_state[0];
A1L56_p2_out = !inner_state[3] & !inner_state[0] & inner_state[2] & phase3;
A1L56_p3_out = !inner_state[3] & !phase3 & sda_buf;
A1L56_p4_out = !inner_state[3] & !inner_state[0] & sda_buf & !inner_state[1];
A1L56_or_out = A1L56_p1_out # A1L56_p2_out # A1L56_p3_out # A1L56_p4_out;
A1L56 = A1L56_or_out;


--A1L66 is Mux~17798 at LC33
A1L66_p1_out = A1L251 & !inner_state[1] & !inner_state[2] & !phase3 & phase0;
A1L66_p2_out = !inner_state[1] & !inner_state[2] & !phase3 & !phase0 & sda_buf;
A1L66_or_out = A1L66_p1_out # A1L66_p2_out # !inner_state[3];
A1L66 = A1L66_or_out;


--A1L76 is Mux~17805 at LC56
A1L76_p0_out = !A1L36 & !i2c_state[2] & i2c_state[0] & !A1L26 & A1L56 & A1L66;
A1L76_p1_out = sda_buf & A1L36;
A1L76_p2_out = sda_buf & A1L46;
A1L76_p3_out = !i2c_state[2] & !i2c_state[0] & A1L26;
A1L76_p4_out = A1L36 & !i2c_state[2] & !i2c_state[0];
A1L76_or_out = A1L58 # A1L76_p0_out # A1L76_p1_out # A1L76_p2_out # A1L76_p3_out # A1L76_p4_out;
A1L76 = A1L76_or_out;


--A1L86 is Mux~17806 at SEXP26
A1L86 = EXP(!inner_state[2] & !inner_state[0] & !inner_state[1]);


--A1L96 is Mux~17808 at SEXP25
A1L96 = EXP(!i2c_state[0] & !inner_state[0]);


--A1L07 is Mux~17809 at SEXP24
A1L07 = EXP(phase0 & i2c_state[1]);


--A1L17 is Mux~17810 at SEXP20
A1L17 = EXP(!inner_state[1] & !link);


--A1L27 is Mux~17811 at SEXP18
A1L27 = EXP(phase0 & !A1L251);


--A1L37 is Mux~17817 at LC23
A1L37_p0_out = sda_buf & !phase3 & A1L27 & A1L96;
A1L37_p1_out = A1L49 & !i2c_state[1] & sda_buf & !phase3;
A1L37_p2_out = sda_buf & A1L07 & !inner_state[0] & inner_state[3];
A1L37_p3_out = !i2c_state[1] & phase3 & !inner_state[0] & !inner_state[3] & A1L17 & !i2c_state[0] & !inner_state[2];
A1L37_p4_out = A1L49 & sda_buf & inner_state[3];
A1L37_or_out = A1L88 # A1L37_p0_out # A1L37_p1_out # A1L37_p2_out # A1L37_p3_out # A1L37_p4_out;
A1L37 = A1L37_or_out;


--A1L47 is Mux~17823 at LC36
A1L47_p0_out = !inner_state[3] & !inner_state[0] & !i2c_state[1] & !i2c_state[0] & !inner_state[2] & phase3 & link;
A1L47_p1_out = sda_buf & inner_state[3] & !inner_state[0];
A1L47_p2_out = inner_state[3] & inner_state[0] & A1L251 & phase0 & !inner_state[1] & !i2c_state[1] & !i2c_state[0] & !inner_state[2];
A1L47_p3_out = !inner_state[3] & inner_state[0] & inner_state[1] & !i2c_state[1] & !i2c_state[0] & inner_state[2] & phase3;
A1L47_p4_out = !inner_state[3] & !inner_state[0] & inner_state[1] & !i2c_state[1] & !i2c_state[0] & !inner_state[2] & phase3;
A1L47_or_out = A1L09 # A1L47_p0_out # A1L47_p1_out # A1L47_p2_out # A1L47_p3_out # A1L47_p4_out;
A1L47 = A1L47_or_out;


--sda_buf is sda_buf at LC38
sda_buf_p0_out = !main_state[0] & main_state[1] & i2c_state[2] & !A1L47;
sda_buf_p1_out = !A1L76 & main_state[0] & !main_state[1];
sda_buf_p2_out = main_state[0] & main_state[1] & !sda_buf;
sda_buf_p3_out = !main_state[0] & main_state[1] & !A1L37 & !i2c_state[2];
sda_buf_or_out = sda_buf_p0_out # sda_buf_p1_out # sda_buf_p2_out # sda_buf_p3_out;
sda_buf_reg_input = !(sda_buf_or_out);
sda_buf = DFFE(sda_buf_reg_input, GLOBAL(clk), , rst, );


--readData_reg[3] is readData_reg[3] at LC68
readData_reg[3]_p0_out = !readData_reg[2] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[3] & !inner_state[0] & !inner_state[1];
readData_reg[3]_p1_out = readData_reg[2] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[3];
readData_reg[3]_p2_out = !readData_reg[2] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[3] & inner_state[0];
readData_reg[3]_p3_out = !readData_reg[2] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[3] & inner_state[1];
readData_reg[3]_p4_out = !readData_reg[2] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[3];
readData_reg[3]_or_out = A1L601 # readData_reg[3]_p0_out # readData_reg[3]_p1_out # readData_reg[3]_p2_out # readData_reg[3]_p3_out # readData_reg[3]_p4_out;
readData_reg[3]_reg_input = readData_reg[3]_or_out;
readData_reg[3] = TFFE(readData_reg[3]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[4] is readData_reg[4] at LC108
readData_reg[4]_p0_out = !readData_reg[3] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[4] & !inner_state[0] & !inner_state[1];
readData_reg[4]_p1_out = readData_reg[3] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[4];
readData_reg[4]_p2_out = !readData_reg[3] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[4] & inner_state[0];
readData_reg[4]_p3_out = !readData_reg[3] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[4] & inner_state[1];
readData_reg[4]_p4_out = !readData_reg[3] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[4];
readData_reg[4]_or_out = A1L801 # readData_reg[4]_p0_out # readData_reg[4]_p1_out # readData_reg[4]_p2_out # readData_reg[4]_p3_out # readData_reg[4]_p4_out;
readData_reg[4]_reg_input = readData_reg[4]_or_out;
readData_reg[4] = TFFE(readData_reg[4]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[5] is readData_reg[5] at LC106
readData_reg[5]_p0_out = !readData_reg[4] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[5] & !inner_state[0] & !inner_state[1];
readData_reg[5]_p1_out = readData_reg[4] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[5];
readData_reg[5]_p2_out = !readData_reg[4] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[5] & inner_state[0];
readData_reg[5]_p3_out = !readData_reg[4] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[5] & inner_state[1];
readData_reg[5]_p4_out = !readData_reg[4] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[5];
readData_reg[5]_or_out = A1L011 # readData_reg[5]_p0_out # readData_reg[5]_p1_out # readData_reg[5]_p2_out # readData_reg[5]_p3_out # readData_reg[5]_p4_out;
readData_reg[5]_reg_input = readData_reg[5]_or_out;
readData_reg[5] = TFFE(readData_reg[5]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--main_state[0] is main_state[0] at LC15
main_state[0]_p0_out = main_state[0] & !i2c_state[2] & !i2c_state[0] & inner_state[0] & inner_state[1];
main_state[0]_p1_out = main_state[0] & !i2c_state[1] & !i2c_state[2] & inner_state[2];
main_state[0]_p2_out = main_state[0] & !i2c_state[2] & !inner_state[3] & !i2c_state[0];
main_state[0]_p3_out = main_state[0] & !i2c_state[2] & inner_state[2] & !i2c_state[0];
main_state[0]_p4_out = main_state[0] & !i2c_state[2] & !i2c_state[0] & !inner_state[0] & !inner_state[1];
main_state[0]_or_out = A1L29 # main_state[0]_p0_out # main_state[0]_p1_out # main_state[0]_p2_out # main_state[0]_p3_out # main_state[0]_p4_out;
main_state[0]_reg_input = main_state[0]_or_out;
main_state[0] = DFFE(main_state[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[6] is readData_reg[6] at LC110
readData_reg[6]_p0_out = !readData_reg[5] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[6] & !inner_state[0] & !inner_state[1];
readData_reg[6]_p1_out = readData_reg[5] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[6];
readData_reg[6]_p2_out = !readData_reg[5] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[6] & inner_state[0];
readData_reg[6]_p3_out = !readData_reg[5] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[6] & inner_state[1];
readData_reg[6]_p4_out = !readData_reg[5] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[6];
readData_reg[6]_or_out = A1L211 # readData_reg[6]_p0_out # readData_reg[6]_p1_out # readData_reg[6]_p2_out # readData_reg[6]_p3_out # readData_reg[6]_p4_out;
readData_reg[6]_reg_input = readData_reg[6]_or_out;
readData_reg[6] = TFFE(readData_reg[6]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--start_delaycnt is start_delaycnt at LC3
start_delaycnt_p1_out = !rd_input & !cnt_delay[18] & !cnt_delay[10] & !cnt_delay[8] & !cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & !cnt_delay[13] & !cnt_delay[12] & !start_delaycnt;
start_delaycnt_p2_out = !cnt_delay[18] & !cnt_delay[10] & !cnt_delay[8] & !cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & !cnt_delay[13] & !cnt_delay[12] & !start_delaycnt & !wr_input;
start_delaycnt_p4_out = cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[12] & start_delaycnt;
start_delaycnt_or_out = start_delaycnt_p1_out # start_delaycnt_p2_out # start_delaycnt_p4_out;
start_delaycnt_reg_input = start_delaycnt_or_out;
start_delaycnt_p3_out = !main_state[1] & !main_state[0];
start_delaycnt = TFFE(start_delaycnt_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt_p3_out);


--cnt_delay[0] is cnt_delay[0] at LC11
cnt_delay[0]_p1_out = cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & cnt_delay[13] & cnt_delay[12] & !cnt_delay[0];
cnt_delay[0]_or_out = cnt_delay[0]_p1_out;
cnt_delay[0]_reg_input = !cnt_delay[0]_or_out;
cnt_delay[0] = TFFE(cnt_delay[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--readData_reg[7] is readData_reg[7] at LC112
readData_reg[7]_p0_out = !readData_reg[6] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[7] & !inner_state[0] & !inner_state[1];
readData_reg[7]_p1_out = readData_reg[6] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[7];
readData_reg[7]_p2_out = !readData_reg[6] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[7] & inner_state[0];
readData_reg[7]_p3_out = !readData_reg[6] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[7] & inner_state[1];
readData_reg[7]_p4_out = !readData_reg[6] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[7];
readData_reg[7]_or_out = A1L411 # readData_reg[7]_p0_out # readData_reg[7]_p1_out # readData_reg[7]_p2_out # readData_reg[7]_p3_out # readData_reg[7]_p4_out;
readData_reg[7]_reg_input = readData_reg[7]_or_out;
readData_reg[7] = TFFE(readData_reg[7]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L811 is reduce_or~2460 at LC102
A1L811_p0_out = en_xhdl3[0] & readData_reg[7];
A1L811_p1_out = en_xhdl3[1] & writeData_reg[1] & !writeData_reg[3] & !writeData_reg[2] & !writeData_reg[0];
A1L811_p2_out = !en_xhdl3[1] & readData_reg[2] & !readData_reg[1] & readData_reg[3] & !readData_reg[0];
A1L811_p3_out = readData_reg[2] & readData_reg[1] & !readData_reg[3] & readData_reg[0] & en_xhdl3[0];
A1L811_p4_out = !en_xhdl3[1] & !en_xhdl3[0];
A1L811_or_out = A1L631 # A1L811_p0_out # A1L811_p1_out # A1L811_p2_out # A1L811_p3_out # A1L811_p4_out;
A1L811 = A1L811_or_out;


--cnt_delay[1] is cnt_delay[1] at LC12
cnt_delay[1]_or_out = cnt_delay[0];
cnt_delay[1]_reg_input = cnt_delay[1] $ cnt_delay[1]_or_out;
cnt_delay[1] = DFFE(cnt_delay[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L911 is reduce_or~2461 at SEXP96
A1L911 = EXP(readData_reg[1] & !readData_reg[2]);


--A1L021 is reduce_or~2462 at SEXP95
A1L021 = EXP(!readData_reg[1] & readData_reg[2]);


--A1L121 is reduce_or~2463 at SEXP94
A1L121 = EXP(!writeData_reg[2] & !writeData_reg[1]);


--A1L221 is reduce_or~2464 at SEXP92
A1L221 = EXP(writeData_reg[2] & writeData_reg[1]);


--A1L321 is reduce_or~2465 at SEXP89
A1L321 = EXP(!readData_reg[1] & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & readData_reg[2] & en_xhdl3[0] & !readData_reg[3]);


--A1L421 is reduce_or~2466 at SEXP87
A1L421 = EXP(!en_xhdl3[0] & !en_xhdl3[1]);


--A1L521 is reduce_or~2467 at SEXP83