i2c.fit.eqn

CPLD VHDL CODE非常好的参考资料

--en_xhdl3[1] is en_xhdl3[1] at LC117
en_xhdl3[1]_p1_out = C1_dffs[11] & C1_dffs[10] & C1_dffs[9] & C1_dffs[8] & C1_dffs[7] & C1_dffs[6] & C1_dffs[5] & C1_dffs[4] & C1_dffs[3] & C1_dffs[2] & C1_dffs[1] & C1_dffs[0];
en_xhdl3[1]_or_out = en_xhdl3[1]_p1_out;
en_xhdl3[1]_reg_input = en_xhdl3[1]_or_out;
en_xhdl3[1] = TFFE(en_xhdl3[1]_reg_input, GLOBAL(clk), , rst, );


--clk_div[6] is clk_div[6] at LC25
clk_div[6]_p1_out = !clk_div[7] & C1_dffs[0] & clk_div[5] & !clk_div[4] & !clk_div[3] & !clk_div[2] & clk_div[6] & clk_div[1];
clk_div[6]_p2_out = C1_dffs[0] & clk_div[5] & clk_div[4] & clk_div[3] & clk_div[2] & clk_div[1];
clk_div[6]_or_out = clk_div[6]_p1_out # clk_div[6]_p2_out;
clk_div[6]_reg_input = clk_div[6]_or_out;
clk_div[6] = TFFE(clk_div[6]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--phase0 is phase0 at LC30
phase0_p1_out = !phase0 & C1_dffs[0] & clk_div[5] & !clk_div[3] & !clk_div[7] & !clk_div[2] & clk_div[6] & !clk_div[4] & clk_div[1];
phase0_or_out = phase0_p1_out;
phase0_reg_input = phase0_or_out;
phase0 = DFFE(phase0_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--phase1 is phase1 at LC27
phase1_p1_out = !phase1 & !clk_div[6] & clk_div[4] & !clk_div[1] & !C1_dffs[0] & !clk_div[5] & clk_div[3] & !clk_div[7] & !clk_div[2];
phase1_or_out = phase1_p1_out;
phase1_reg_input = phase1_or_out;
phase1 = DFFE(phase1_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--phase2 is phase2 at LC26
phase2_p1_out = !phase2 & C1_dffs[0] & clk_div[5] & !clk_div[3] & !clk_div[7] & !clk_div[2] & !clk_div[6] & clk_div[4] & !clk_div[1];
phase2_or_out = phase2_p1_out;
phase2_reg_input = phase2_or_out;
phase2 = DFFE(phase2_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--phase3 is phase3 at LC29
phase3_p1_out = !phase3 & clk_div[6] & !clk_div[4] & clk_div[1] & !C1_dffs[0] & !clk_div[5] & clk_div[3] & !clk_div[7] & !clk_div[2];
phase3_or_out = phase3_p1_out;
phase3_reg_input = phase3_or_out;
phase3 = DFFE(phase3_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--inner_state[1] is inner_state[1] at LC19
inner_state[1]_p0_out = !main_state[0] & !main_state[1] & inner_state[1];
inner_state[1]_p1_out = !main_state[0] & i2c_state[1] & main_state[1] & inner_state[0] & phase3 & !i2c_state[2] & i2c_state[0] & !inner_state[2] & !inner_state[1];
inner_state[1]_p2_out = main_state[0] & i2c_state[1] & !main_state[1] & inner_state[0] & phase3 & !i2c_state[2] & !i2c_state[0] & !inner_state[2] & !inner_state[1] & !phase1;
inner_state[1]_p3_out = !main_state[0] & main_state[1] & inner_state[0] & phase3 & !i2c_state[2] & i2c_state[0] & !inner_state[3];
inner_state[1]_p4_out = !main_state[0] & !i2c_state[1] & main_state[1] & inner_state[0] & phase3 & !i2c_state[0] & !inner_state[3];
inner_state[1]_or_out = A1L641 # inner_state[1]_p0_out # inner_state[1]_p1_out # inner_state[1]_p2_out # inner_state[1]_p3_out # inner_state[1]_p4_out;
inner_state[1]_reg_input = inner_state[1]_or_out;
inner_state[1] = TFFE(inner_state[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L65 is Mux~17742 at LC44
A1L65_p0_out = main_state[1] & !main_state[0] & !i2c_state[1] & !i2c_state[0] & !inner_state[0] & !inner_state[3] & phase1 & !inner_state[1] & !inner_state[2];
A1L65_p1_out = link & main_state[1] & !main_state[0] & i2c_state[1];
A1L65_p2_out = link & main_state[1] & !main_state[0] & i2c_state[2] & i2c_state[0];
A1L65_p3_out = link & main_state[1] & !main_state[0] & !phase3;
A1L65_p4_out = main_state[1] & !main_state[0] & !i2c_state[1] & !i2c_state[0] & phase3 & inner_state[0] & !inner_state[3];
A1L65_or_out = A1L67 # A1L65_p0_out # A1L65_p1_out # A1L65_p2_out # A1L65_p3_out # A1L65_p4_out;
A1L65 = A1L65_or_out;


--A1L75 is Mux~17743 at LC54
A1L75_p0_out = phase3 & !inner_state[0] & inner_state[3] & !i2c_state[0] & !main_state[1] & !i2c_state[2] & link & !inner_state[2] & !inner_state[1];
A1L75_p2_out = main_state[0] & phase3 & inner_state[0] & !inner_state[3] & !i2c_state[0] & !main_state[1] & !i2c_state[2] & !link;
A1L75_p3_out = !main_state[0] & link;
A1L75_p4_out = phase3 & !inner_state[0] & inner_state[3] & !main_state[1] & !i2c_state[2] & link & !i2c_state[1] & !inner_state[2] & !inner_state[1];
A1L75_or_out = A1L87 # A1L75_p0_out # A1L75_p2_out # A1L75_p3_out # A1L75_p4_out;
A1L75 = link $ A1L75_or_out;


--link is link at LC24
link_p1_out = !A1L65 & !A1L75;
link_or_out = link_p1_out;
link_reg_input = !(link_or_out);
link = DFFE(link_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L85 is Mux~17753 at SEXP60
A1L85 = EXP(!i2c_state[1] & !i2c_state[0] & link);


--A1L95 is Mux~17754 at SEXP55
A1L95 = EXP(i2c_state[1] & i2c_state[0]);


--A1L06 is Mux~17755 at SEXP52
A1L06 = EXP(main_state[1] & !i2c_state[0]);


--A1L16 is Mux~17756 at SEXP49
A1L16 = EXP(!inner_state[1] & !inner_state[2]);


--inner_state[0] is inner_state[0] at LC51
inner_state[0]_p0_out = !inner_state[0] & inner_state[3] & A1L16;
inner_state[0]_p1_out = i2c_state[1] & !inner_state[0] & i2c_state[0] & !main_state[1];
inner_state[0]_p2_out = !inner_state[0] & A1L85 & !inner_state[3] & !inner_state[2] & !inner_state[1];
inner_state[0]_p3_out = inner_state[0] & !main_state[1] & !inner_state[3] & A1L95 & phase3 & !i2c_state[2];
inner_state[0]_p4_out = !inner_state[0] & i2c_state[2] & A1L06;
inner_state[0]_or_out = A1L08 # inner_state[0]_p0_out # inner_state[0]_p1_out # inner_state[0]_p2_out # inner_state[0]_p3_out # inner_state[0]_p4_out;
inner_state[0]_reg_input = !(inner_state[0]_or_out);
inner_state[0] = DFFE(inner_state[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--inner_state[3] is inner_state[3] at LC5
inner_state[3]_p0_out = !main_state[0] & !main_state[1] & inner_state[3];
inner_state[3]_p1_out = !i2c_state[0] & inner_state[1] & inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & !main_state[0] & main_state[1] & !inner_state[3];
inner_state[3]_p2_out = !i2c_state[0] & !inner_state[1] & !inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & !main_state[0] & inner_state[3];
inner_state[3]_p3_out = !inner_state[1] & !inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & !main_state[0] & inner_state[3] & !i2c_state[2];
inner_state[3]_p4_out = !inner_state[1] & !inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & !main_state[1] & inner_state[3] & !i2c_state[2];
inner_state[3]_or_out = A1L741 # inner_state[3]_p0_out # inner_state[3]_p1_out # inner_state[3]_p2_out # inner_state[3]_p3_out # inner_state[3]_p4_out;
inner_state[3]_reg_input = inner_state[3]_or_out;
inner_state[3] = TFFE(inner_state[3]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--i2c_state[0] is i2c_state[0] at LC7
i2c_state[0]_p1_out = main_state[1] & !i2c_state[1] & inner_state[3] & !inner_state[1] & !inner_state[2] & inner_state[0] & !main_state[0] & phase3 & !i2c_state[2];
i2c_state[0]_p2_out = main_state[1] & !i2c_state[1] & inner_state[3] & !inner_state[1] & !inner_state[2] & inner_state[0] & !main_state[0] & phase3 & !i2c_state[0];
i2c_state[0]_p3_out = !main_state[1] & !i2c_state[1] & inner_state[3] & !inner_state[1] & !inner_state[2] & inner_state[0] & main_state[0] & phase3 & !i2c_state[2];
i2c_state[0]_p4_out = !main_state[1] & !main_state[0] & i2c_state[0];
i2c_state[0]_or_out = i2c_state[0]_p1_out # i2c_state[0]_p2_out # i2c_state[0]_p3_out # i2c_state[0]_p4_out;
i2c_state[0]_reg_input = i2c_state[0]_or_out;
i2c_state[0] = TFFE(i2c_state[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--i2c_state[2] is i2c_state[2] at LC82
i2c_state[2]_p1_out = main_state[1] & !main_state[0] & inner_state[3] & !inner_state[1] & !inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & i2c_state[0] & !i2c_state[2];
i2c_state[2]_p2_out = !main_state[1] & !main_state[0] & i2c_state[2];
i2c_state[2]_p3_out = !main_state[0] & inner_state[3] & !inner_state[1] & !inner_state[2] & inner_state[0] & phase3 & !i2c_state[1] & !i2c_state[0] & i2c_state[2];
i2c_state[2]_or_out = i2c_state[2]_p1_out # i2c_state[2]_p2_out # i2c_state[2]_p3_out;
i2c_state[2]_reg_input = i2c_state[2]_or_out;
i2c_state[2] = TFFE(i2c_state[2]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[0] is readData_reg[0] at LC61
readData_reg[0]_p0_out = !A1L251 & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[0] & !inner_state[0] & !inner_state[1];
readData_reg[0]_p1_out = A1L251 & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[0];
readData_reg[0]_p2_out = !A1L251 & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[0] & inner_state[0];
readData_reg[0]_p3_out = !A1L251 & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[0] & inner_state[1];
readData_reg[0]_p4_out = !A1L251 & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[0];
readData_reg[0]_or_out = A1L351 # readData_reg[0]_p0_out # readData_reg[0]_p1_out # readData_reg[0]_p2_out # readData_reg[0]_p3_out # readData_reg[0]_p4_out;
readData_reg[0]_reg_input = readData_reg[0]_or_out;
readData_reg[0] = TFFE(readData_reg[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[1] is readData_reg[1] at LC104
readData_reg[1]_p0_out = !readData_reg[0] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[1] & !inner_state[0] & !inner_state[1];
readData_reg[1]_p1_out = readData_reg[0] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[1];
readData_reg[1]_p2_out = !readData_reg[0] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[1] & inner_state[0];
readData_reg[1]_p3_out = !readData_reg[0] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[1] & inner_state[1];
readData_reg[1]_p4_out = !readData_reg[0] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[1];
readData_reg[1]_or_out = A1L201 # readData_reg[1]_p0_out # readData_reg[1]_p1_out # readData_reg[1]_p2_out # readData_reg[1]_p3_out # readData_reg[1]_p4_out;
readData_reg[1]_reg_input = readData_reg[1]_or_out;
readData_reg[1] = TFFE(readData_reg[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[2] is readData_reg[2] at LC70
readData_reg[2]_p0_out = !readData_reg[1] & phase1 & i2c_state[1] & !inner_state[2] & inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[2] & !inner_state[0] & !inner_state[1];
readData_reg[2]_p1_out = readData_reg[1] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & !readData_reg[2];
readData_reg[2]_p2_out = !readData_reg[1] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[2] & inner_state[0];
readData_reg[2]_p3_out = !readData_reg[1] & phase1 & i2c_state[1] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[2] & inner_state[1];
readData_reg[2]_p4_out = !readData_reg[1] & phase1 & i2c_state[1] & inner_state[2] & !inner_state[3] & main_state[1] & !main_state[0] & !i2c_state[2] & i2c_state[0] & readData_reg[2];
readData_reg[2]_or_out = A1L401 # readData_reg[2]_p0_out # readData_reg[2]_p1_out # readData_reg[2]_p2_out # readData_reg[2]_p3_out # readData_reg[2]_p4_out;
readData_reg[2]_reg_input = readData_reg[2]_or_out;
readData_reg[2] = TFFE(readData_reg[2]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L26 is Mux~17780 at LC64
A1L26_p0_out = !i2c_state[1] & !i2c_state[0] & !inner_state[3] & phase3 & !inner_state[2] & !inner_state[0] & link;
A1L26_p1_out = sda_buf & !i2c_state[1] & !i2c_state[0] & inner_state[3] & !phase3 & !phase0;
A1L26_p2_out = !i2c_state[1] & !i2c_state[0] & inner_state[3] & !phase3 & phase0 & !inner_state[1] & !inner_state[2] & inner_state[0] & A1L251;
A1L26_p3_out = sda_buf & !i2c_state[1] & !i2c_state[0] & !inner_state[3] & !phase3 & inner_state[0];
A1L26_p4_out = !i2c_state[1] & !i2c_state[0] & !inner_state[3] & phase3 & inner_state[1] & !inner_state[2] & !inner_state[0];
A1L26_or_out = A1L28 # A1L26_p0_out # A1L26_p1_out # A1L26_p2_out # A1L26_p3_out # A1L26_p4_out;
A1L26 = A1L26_or_out;


--A1L36 is Mux~17786 at LC59
A1L36_p0_out = i2c_state[1] & inner_state[3] & sda_buf & !inner_state[0];
A1L36_p1_out = !phase0 & phase1 & i2c_state[1] & inner_state[3] & sda_buf;
A1L36_p2_out = phase1 & i2c_state[1] & inner_state[3] & inner_state[1] & !inner_state[2] & !inner_state[0];
A1L36_p3_out = i2c_state[1] & inner_state[3] & sda_buf & inner_state[1];
A1L36_p4_out = i2c_state[1] & inner_state[3] & sda_buf & inner_state[2];
A1L36_or_out = A1L48 # A1L36_p0_out # A1L36_p1_out # A1L36_p2_out # A1L36_p3_out # A1L36_p4_out;
A1L36 = A1L36_or_out;


--A1L46 is Mux~17790 at LC81
A1L46_p1_out = inner_state[1] & inner_state[3] & i2c_state[0];
A1L46_p2_out = inner_state[3] & i2c_state[0] & inner_state[2];
A1L46_p3_out = inner_state[3] & i2c_state[0] & !inner_state[0];
A1L46_or_out = A1L46_p1_out # A1L46_p2_out # A1L46_p3_out;
A1L46 = A1L46_or_out;