lcd.tan.qmsg

CPLD VHDL CODE非常好的参考资料

{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[0\] state\[9\] 55.000 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[0\]\" through register \"state\[9\]\" is 55.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 30.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 30.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clkcnt\[17\] 2 REG LC24 18 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC24; Fanout = 18; REG Node = 'clkcnt\[17\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "1.000 ns" { clk clkcnt[17] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns clkdiv 3 REG LC15 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC15; Fanout = 3; REG Node = 'clkdiv'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "9.000 ns" { clkcnt[17] clkdiv } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns clk_int 4 REG LC99 21 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC99; Fanout = 21; REG Node = 'clk_int'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "9.000 ns" { clkdiv clk_int } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 30.000 ns state\[9\] 5 REG LC85 185 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 30.000 ns; Loc. = LC85; Fanout = 185; REG Node = 'state\[9\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "8.000 ns" { clk_int state[9] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.000 ns 80.00 % " "Info: Total cell delay = 24.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 20.00 % " "Info: Total interconnect delay = 6.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "30.000 ns" { clk clkcnt[17] clkdiv clk_int state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { clk clk~out clkcnt[17] clkdiv clk_int state[9] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.000 ns + Longest register pin " "Info: + Longest register to pin delay is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[9\] 1 REG LC85 185 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC85; Fanout = 185; REG Node = 'state\[9\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "" { state[9] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns data~2556 2 COMB LC54 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC54; Fanout = 1; COMB Node = 'data~2556'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "8.000 ns" { state[9] data~2556 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns data~2558 3 COMB LC55 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC55; Fanout = 1; COMB Node = 'data~2558'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "1.000 ns" { data~2556 data~2558 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 11.000 ns data~2459 4 COMB LC56 1 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 11.000 ns; Loc. = LC56; Fanout = 1; COMB Node = 'data~2459'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "2.000 ns" { data~2558 data~2459 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns data~2468 5 COMB LC83 1 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC83; Fanout = 1; COMB Node = 'data~2468'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "9.000 ns" { data~2459 data~2468 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns data\[0\] 6 PIN PIN_54 0 " "Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'data\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "4.000 ns" { data~2468 data[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.000 ns 83.33 % " "Info: Total cell delay = 20.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.67 % " "Info: Total interconnect delay = 4.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "24.000 ns" { state[9] data~2556 data~2558 data~2459 data~2468 data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { state[9] data~2556 data~2558 data~2459 data~2468 data[0] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "30.000 ns" { clk clkcnt[17] clkdiv clk_int state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { clk clk~out clkcnt[17] clkdiv clk_int state[9] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "24.000 ns" { state[9] data~2556 data~2558 data~2459 data~2468 data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { state[9] data~2556 data~2558 data~2459 data~2468 data[0] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 13 19:29:45 2005 " "Info: Processing ended: Tue Dec 13 19:29:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}