📄 lcd.tan.qmsg
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "21 " "Warning: Found 21 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_int " "Info: Detected ripple clock \"clk_int\" as buffer" { } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_int" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv " "Info: Detected ripple clock \"clkdiv\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkdiv" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[1\] " "Info: Detected ripple clock \"clkcnt\[1\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[1\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[2\] " "Info: Detected ripple clock \"clkcnt\[2\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[2\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[3\] " "Info: Detected ripple clock \"clkcnt\[3\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[3\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[4\] " "Info: Detected ripple clock \"clkcnt\[4\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[4\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[5\] " "Info: Detected ripple clock \"clkcnt\[5\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[5\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[18\] " "Info: Detected ripple clock \"clkcnt\[18\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[18\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[6\] " "Info: Detected ripple clock \"clkcnt\[6\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[6\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[7\] " "Info: Detected ripple clock \"clkcnt\[7\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[7\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[8\] " "Info: Detected ripple clock \"clkcnt\[8\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[8\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[9\] " "Info: Detected ripple clock \"clkcnt\[9\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[9\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[10\] " "Info: Detected ripple clock \"clkcnt\[10\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[10\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[11\] " "Info: Detected ripple clock \"clkcnt\[11\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[11\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[12\] " "Info: Detected ripple clock \"clkcnt\[12\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[12\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[13\] " "Info: Detected ripple clock \"clkcnt\[13\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[13\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[14\] " "Info: Detected ripple clock \"clkcnt\[14\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[14\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[15\] " "Info: Detected ripple clock \"clkcnt\[15\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[15\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[16\] " "Info: Detected ripple clock \"clkcnt\[16\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[16\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[17\] " "Info: Detected ripple clock \"clkcnt\[17\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[17\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[0\] " "Info: Detected ripple clock \"clkcnt\[0\]\" as buffer" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[0\]" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clkcnt\[0\] register clkcnt\[10\] 62.5 MHz 16.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 62.5 MHz between source register \"clkcnt\[0\]\" and destination register \"clkcnt\[10\]\" (period= 16.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest register register " "Info: + Longest register to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkcnt\[0\] 1 REG LC13 116 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 116; REG Node = 'clkcnt\[0\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "" { clkcnt[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns clkcnt~718 2 COMB LC1 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 1; COMB Node = 'clkcnt~718'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "8.000 ns" { clkcnt[0] clkcnt~718 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns clkcnt~717 3 COMB LC2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'clkcnt~717'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "1.000 ns" { clkcnt~718 clkcnt~717 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns clkcnt~716 4 COMB LC3 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'clkcnt~716'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "1.000 ns" { clkcnt~717 clkcnt~716 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns clkcnt\[10\] 5 REG LC4 90 " "Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC4; Fanout = 90; REG Node = 'clkcnt\[10\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "1.000 ns" { clkcnt~716 clkcnt[10] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 81.82 % " "Info: Total cell delay = 9.000 ns ( 81.82 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 18.18 % " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "11.000 ns" { clkcnt[0] clkcnt~718 clkcnt~717 clkcnt~716 clkcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clkcnt[0] clkcnt~718 clkcnt~717 clkcnt~716 clkcnt[10] } { 0.000ns 2.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clkcnt\[10\] 2 REG LC4 90 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 90; REG Node = 'clkcnt\[10\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "0.000 ns" { clk clkcnt[10] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "3.000 ns" { clk clkcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clkcnt[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clkcnt\[0\] 2 REG LC13 116 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC13; Fanout = 116; REG Node = 'clkcnt\[0\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "0.000 ns" { clk clkcnt[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "3.000 ns" { clk clkcnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clkcnt[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "3.000 ns" { clk clkcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clkcnt[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "3.000 ns" { clk clkcnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clkcnt[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 73 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "11.000 ns" { clkcnt[0] clkcnt~718 clkcnt~717 clkcnt~716 clkcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clkcnt[0] clkcnt~718 clkcnt~717 clkcnt~716 clkcnt[10] } { 0.000ns 2.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns 1.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "3.000 ns" { clk clkcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clkcnt[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/" "" "3.000 ns" { clk clkcnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clkcnt[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0}
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