📄 buzzer.fit.rpt
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+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 23.38) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 1 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 1 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 4 ;
; 27 - 29 ; 2 ;
+-----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 8.00) ; Number of LABs (Total = 8) ;
+----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 3 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 7 ;
; 2 ; 1 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.88) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC3 ; clk, rst, state[1], out_bit_tmp~342, Mux~9688, state[2], Mux~9695, state[0], out_bit_tmp~346, Mux~9700, Mux~9707, clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3] ; out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, out_bit ;
; B ; LC18 ; clk, rst, Mux~9718, clk_div2[0], state[2], clk_div2[5], clk_div2[4], clk_div2[10], clk_div2[2], clk_div2[8], clk_div2[9], state[0], state[1], clk_div2[12], clk_div2[3], clk_div2[7], clk_div2[6], clk_div2[11], clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3] ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div2[12], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~16, clk_div2[5], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~20, clk_div2[6], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~24, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~23, clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC25 ; clk, rst, Mux~9722, state[0], clk_div2[10], state[1], clk_div2[9], clk_div2[6], clk_div2[1], clk_div2[8], clk_div2[3], clk_div2[7], clk_div2[2], state[2], clk_div2[4], clk_div2[0], clk_div2[5], clk_div2[11], clk_div2[12], clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3], lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2 ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], clk_div2[5], clk_div2[6], clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC27 ; clk, rst, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3], Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5 ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], clk_div2[5], clk_div2[6], clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC23 ; clk, rst, Mux~9726, clk_div2[11], state[0], state[1], state[2], clk_div2[12], clk_div2[0], clk_div2[4], clk_div2[1], clk_div2[9], clk_div2[8], clk_div2[7], clk_div2[2], clk_div2[6], clk_div2[5], clk_div2[3], clk_div2[10], clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3] ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], clk_div2[5], clk_div2[6], clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC28 ; clk, rst, state[0], clk_div2[5], clk_div2[10], clk_div2[2], clk_div2[1], clk_div2[4], state[2], clk_div2[11], state[1], clk_div2[8], clk_div2[12], clk_div2[9], clk_div2[3], clk_div2[7], clk_div2[6], clk_div2[0], clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3] ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~16, clk_div2[5], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~20, clk_div2[6], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~24, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~23, clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC26 ; clk, rst, clk_div2[1], clk_div2[2], clk_div2[8], clk_div2[7], clk_div2[9], clk_div2[5], state[0], clk_div2[3], clk_div2[11], clk_div2[10], clk_div2[6], clk_div2[12], clk_div2[4], state[2], state[1], clk_div2[0], clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3] ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~16, clk_div2[5], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~20, clk_div2[6], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~24, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~23, clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9728, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC21 ; clk, rst, Mux~9730, clk_div2[3], clk_div2[2], state[2], clk_div2[5], clk_div2[11], clk_div2[10], clk_div2[9], clk_div2[8], clk_div2[4], state[0], clk_div2[7], state[1], clk_div2[6], clk_div2[12], clk_div2[0], clk_div2[1], clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3] ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~16, clk_div2[5], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~20, clk_div2[6], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~24, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~23, clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9728, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC30 ; clk, rst, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~24, clk_div1[2], clk_div1[1], clk_div1[0], clk_div1[3], Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp1, Mux~9677sexp4, Mux~9677sexp5 ; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~2, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~6, clk_div2[12], clk_div2[1], clk_div2[11], clk_div2[10], clk_div2[0], clk_div2[2], clk_div2[3], clk_div2[4], clk_div2[5], clk_div2[6], lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~24, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~23, clk_div2[8], out_bit_tmp~342, Mux~9688, Mux~9695, out_bit_tmp~346, Mux~9700, Mux~9707, Mux~9718, Mux~9722, Mux~9726, Mux~9730, Mux~9736, Mux~9738, Mux~9742, Mux~9747, Mux~9621sexp1, Mux~9621sexp2, Mux~9621sexp3, Mux~9621sexp4, Mux~9621sexp5, Mux~9677sexp4, Mux~9677sexp5 ;
; B ; LC31 ; clk_div2[9], clk_div2[3], clk_div2[11], clk_div2[10], clk_div2[7], clk_div2[6], clk_div2[12], clk_div2[0], clk_div2[8], clk_div2[2], clk_div2[4], state[0], state[1], clk_div2[5], clk_div2[1], out_bit_tmp ; out_bit_tmp ;
; B ; LC32 ; state[0], clk_div2[5], clk_div2[4], clk_div2[12], clk_div2[9], clk_div2[3], clk_div2[0], clk_div2[7], clk_div2[6], clk_div2[11], clk_div2[1], clk_div2[8], state[1], clk_div2[10], clk_div2[2], out_bit_tmp ; out_bit_tmp ;
; B ; LC17 ; clk_div2[0], clk_div2[1], state[2], clk_div2[5], clk_div2[4], clk_div2[10], clk_div2[2], clk_div2[8], clk_div2[9], state[0], state[1], clk_div2[12], clk_div2[3], clk_div2[7], clk_div2[6], clk_div2[11] ; clk_div2[1] ;
; B ; LC24 ; state[0], clk_div2[10], state[1], clk_div2[9], clk_div2[6], clk_div2[1], clk_div2[8], clk_div2[3], clk_div2[7], clk_div2[2], state[2], clk_div2[4], clk_div2[0], clk_div2[5], clk_div2[11], clk_div2[12] ; clk_div2[11] ;
; B ; LC20 ; Mux~9728, clk_div2[3], clk_div2[1], state[2], clk_div2[5], clk_div2[11], clk_div2[10], clk_div2[9], clk_div2[8], clk_div2[4], state[0], clk_div2[7], state[1], clk_div2[6], clk_div2[12], clk_div2[0], clk_div2[2] ; clk_div2[3] ;
; B ; LC19 ; clk_div2[3], clk_div2[2] ⌨️ 快捷键说明
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