buzzer.fit.eqn

CPLD VHDL CODE非常好的参考资料

--G6L1 is lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~23 at LC45
G6L1_p1_out = clk_div2[7] & clk_div2[6] & clk_div2[5] & clk_div2[4] & clk_div2[2] & clk_div2[3] & clk_div2[0] & clk_div2[1];
G6L1_or_out = !clk_div2[8];
G6L1 = G6L1_p1_out $ G6L1_or_out;


--clk_div2[8] is clk_div2[8] at LC40
clk_div2[8]_p0_out = !state[0] & !clk_div2[10] & !state[2] & !clk_div2[5] & !clk_div2[2] & clk_div2[4] & clk_div2[6] & clk_div2[7] & clk_div2[3] & clk_div2[9] & clk_div2[11] & clk_div2[1] & state[1] & !clk_div2[0] & !clk_div2[12] & clk_div2[8];
clk_div2[8]_p2_out = state[0] & clk_div2[10] & state[2] & clk_div2[5] & clk_div2[2] & clk_div2[4] & clk_div2[6] & !clk_div2[7] & !clk_div2[3] & clk_div2[9] & !clk_div2[11] & clk_div2[1] & state[1] & clk_div2[0] & !clk_div2[12] & clk_div2[8];
clk_div2[8]_p4_out = !state[0] & !clk_div2[10] & state[2] & clk_div2[5] & clk_div2[2] & clk_div2[4] & clk_div2[6] & clk_div2[7] & !clk_div2[3] & !clk_div2[9] & clk_div2[11] & clk_div2[1] & !state[1] & clk_div2[0] & !clk_div2[12] & clk_div2[8];
clk_div2[8]_or_out = A1L04 # clk_div2[8]_p0_out # G6L1 # clk_div2[8]_p2_out # clk_div2[8]_p4_out;
clk_div2[8]_reg_input = !(clk_div2[8]_or_out);
clk_div2[8]_p3_out = !clk_div1[2] & !clk_div1[1] & clk_div1[0] & clk_div1[3];
clk_div2[8] = DFFE(clk_div2[8]_reg_input, GLOBAL(clk), GLOBAL(rst), , clk_div2[8]_p3_out);


--A1L34 is out_bit_tmp~342 at LC37
A1L34_p1_out = !clk_div2[10] & !clk_div2[5] & !clk_div2[12] & clk_div2[9] & clk_div2[3] & !clk_div2[0] & clk_div2[7] & clk_div2[6] & clk_div2[11] & clk_div2[1] & clk_div2[4] & clk_div2[8] & !clk_div2[2];
A1L34_or_out = out_bit_tmp;
A1L34 = A1L34_p1_out $ A1L34_or_out;


--A1L82 is Mux~9688 at LC31
A1L82_p0_out = !clk_div2[9] & clk_div2[3] & clk_div2[11] & clk_div2[10] & !clk_div2[7] & clk_div2[6] & !clk_div2[12] & clk_div2[0] & clk_div2[8] & clk_div2[2] & !clk_div2[4] & state[0] & !state[1] & !clk_div2[5] & !clk_div2[1];
A1L82_p2_out = clk_div2[9] & clk_div2[3] & clk_div2[11] & clk_div2[10] & clk_div2[7] & clk_div2[6] & !clk_div2[12] & !clk_div2[0] & !clk_div2[8] & clk_div2[2] & !clk_div2[4] & !state[0] & !state[1] & clk_div2[5] & clk_div2[1];
A1L82_p3_out = state[0] & state[1] & !out_bit_tmp;
A1L82_p4_out = !state[0] & state[1] & out_bit_tmp;
A1L82_or_out = A1L82_p0_out # A1L82_p2_out # A1L82_p3_out # A1L82_p4_out;
A1L82 = out_bit_tmp $ A1L82_or_out;


--A1L92 is Mux~9695 at LC46
A1L92_p2_out = !state[1] & !out_bit_tmp;
A1L92_p3_out = state[1] & clk_div2[9] & !clk_div2[7] & !clk_div2[6] & !clk_div2[1] & clk_div2[4] & clk_div2[8] & !clk_div2[2] & !clk_div2[10] & clk_div2[5] & !clk_div2[3] & clk_div2[11] & !clk_div2[12] & clk_div2[0];
A1L92_or_out = A1L92_p2_out # A1L92_p3_out;
A1L92 = out_bit_tmp $ A1L92_or_out;


--A1L44 is out_bit_tmp~346 at LC48
A1L44_p1_out = !clk_div2[8] & !clk_div2[2] & !clk_div2[4] & !clk_div2[1] & !clk_div2[9] & clk_div2[7] & clk_div2[6] & !clk_div2[10] & clk_div2[5] & !clk_div2[3] & clk_div2[11] & !clk_div2[12] & clk_div2[0];
A1L44_or_out = out_bit_tmp;
A1L44 = A1L44_p1_out $ A1L44_or_out;


--A1L03 is Mux~9700 at LC32
A1L03_p0_out = !state[0] & clk_div2[5] & !clk_div2[4] & !clk_div2[12] & clk_div2[9] & clk_div2[3] & !clk_div2[0] & clk_div2[7] & clk_div2[6] & !clk_div2[11] & !clk_div2[1] & clk_div2[8] & state[1] & clk_div2[10] & !clk_div2[2];
A1L03_p2_out = !state[0] & clk_div2[5] & clk_div2[4] & !clk_div2[12] & !clk_div2[9] & !clk_div2[3] & clk_div2[0] & clk_div2[7] & clk_div2[6] & clk_div2[11] & clk_div2[1] & clk_div2[8] & !state[1] & !clk_div2[10] & clk_div2[2];
A1L03_p3_out = state[0] & state[1] & !out_bit_tmp;
A1L03_p4_out = state[0] & !state[1] & out_bit_tmp;
A1L03_or_out = A1L03_p0_out # A1L03_p2_out # A1L03_p3_out # A1L03_p4_out;
A1L03 = out_bit_tmp $ A1L03_or_out;


--A1L13 is Mux~9707 at LC47
A1L13_p2_out = !state[0] & !out_bit_tmp;
A1L13_p3_out = state[0] & clk_div2[9] & !clk_div2[3] & !clk_div2[11] & clk_div2[1] & clk_div2[10] & !clk_div2[7] & clk_div2[6] & !clk_div2[12] & clk_div2[0] & clk_div2[8] & clk_div2[2] & clk_div2[5] & clk_div2[4];
A1L13_or_out = A1L13_p2_out # A1L13_p3_out;
A1L13 = out_bit_tmp $ A1L13_or_out;


--out_bit_tmp is out_bit_tmp at LC3
out_bit_tmp_p0_out = state[2] & A1L03 & A1L13;
out_bit_tmp_p1_out = state[1] & A1L34 & !A1L82 & !state[2];
out_bit_tmp_p2_out = A1L82 & !state[2] & A1L92;
out_bit_tmp_p4_out = state[2] & state[0] & A1L44 & !A1L03;
out_bit_tmp_or_out = out_bit_tmp_p0_out # out_bit_tmp_p1_out # out_bit_tmp_p2_out # out_bit_tmp_p4_out;
out_bit_tmp_reg_input = out_bit_tmp_or_out;
out_bit_tmp_p3_out = !clk_div1[2] & !clk_div1[1] & clk_div1[0] & clk_div1[3];
out_bit_tmp = DFFE(out_bit_tmp_reg_input, GLOBAL(clk), GLOBAL(rst), , out_bit_tmp_p3_out);


--A1L23 is Mux~9718 at LC17
A1L23_p1_out = clk_div2[0] & clk_div2[1];
A1L23_p2_out = !clk_div2[0] & !clk_div2[1];
A1L23_p3_out = clk_div2[0] & !state[2] & clk_div2[5] & clk_div2[4] & !clk_div2[10] & !clk_div2[2] & clk_div2[8] & clk_div2[9] & state[0] & state[1] & !clk_div2[12] & !clk_div2[3] & !clk_div2[7] & !clk_div2[6] & clk_div2[11];
A1L23 = A1L23_p1_out # A1L23_p2_out # A1L23_p3_out;


--A1L33 is Mux~9722 at LC24
A1L33_p1_out = !state[0] & clk_div2[10] & !state[1] & clk_div2[9] & clk_div2[6] & clk_div2[1] & !clk_div2[8] & clk_div2[3] & clk_div2[7] & clk_div2[2] & !state[2] & !clk_div2[4] & !clk_div2[0] & clk_div2[5] & clk_div2[11] & !clk_div2[12];
A1L33_p2_out = state[0] & !clk_div2[10] & state[1] & clk_div2[9] & !clk_div2[6] & !clk_div2[1] & clk_div2[8] & !clk_div2[3] & !clk_div2[7] & !clk_div2[2] & !state[2] & clk_div2[4] & clk_div2[0] & clk_div2[5] & clk_div2[11] & !clk_div2[12];
A1L33_p3_out = !state[0] & !clk_div2[10] & !state[1] & !clk_div2[9] & clk_div2[6] & clk_div2[1] & clk_div2[8] & !clk_div2[3] & clk_div2[7] & clk_div2[2] & state[2] & clk_div2[4] & clk_div2[0] & clk_div2[5] & clk_div2[11] & !clk_div2[12];
A1L33 = A1L33_p1_out # A1L33_p2_out # A1L33_p3_out;


--A1L43 is Mux~9726 at LC22
A1L43_p1_out = clk_div2[11] & state[0] & !state[1] & !state[2] & !clk_div2[12] & clk_div2[0] & !clk_div2[4] & !clk_div2[1] & !clk_div2[9] & clk_div2[8] & !clk_div2[7] & clk_div2[2] & clk_div2[6] & !clk_div2[5] & clk_div2[3] & clk_div2[10];
A1L43 = A1L43_p1_out;


--A1L53 is Mux~9728 at LC19
A1L53_p1_out = !clk_div2[3] & !clk_div2[2];
A1L53 = A1L53_p1_out;


--A1L63 is Mux~9730 at LC20
A1L63_p0_out = clk_div2[3] & clk_div2[1] & clk_div2[0] & clk_div2[2];
A1L63_p1_out = !clk_div2[3] & !clk_div2[1];
A1L63_p2_out = !clk_div2[3] & state[2] & clk_div2[5] & clk_div2[11] & !clk_div2[10] & !clk_div2[9] & clk_div2[8] & clk_div2[4] & !state[0] & clk_div2[7] & !state[1] & clk_div2[6] & !clk_div2[12];
A1L63_p3_out = !clk_div2[3] & state[2] & clk_div2[5] & !clk_div2[11] & clk_div2[10] & clk_div2[9] & clk_div2[8] & clk_div2[4] & state[0] & !clk_div2[7] & state[1] & clk_div2[6] & !clk_div2[12];
A1L63_p4_out = !clk_div2[3] & !clk_div2[0];
A1L63 = A1L53 # A1L63_p0_out # A1L63_p1_out # A1L63_p2_out # A1L63_p3_out # A1L63_p4_out;


--A1L73 is Mux~9736 at LC33
A1L73_p1_out = clk_div2[3] & clk_div2[1] & !clk_div2[2] & !clk_div2[0] & clk_div2[6] & state[1] & clk_div2[9] & !clk_div2[5] & clk_div2[11] & !state[0] & !clk_div2[10] & clk_div2[7] & !clk_div2[12] & clk_div2[8] & !state[2] & clk_div2[4];
A1L73 = A1L73_p1_out;


--A1L83 is Mux~9738 at LC35
A1L83_p1_out = !clk_div2[10] & !clk_div2[3] & state[2] & !state[1] & !clk_div2[4] & clk_div2[7] & clk_div2[6] & clk_div2[11] & !clk_div2[9] & !clk_div2[1] & !clk_div2[2] & clk_div2[0] & !clk_div2[8] & state[0] & !clk_div2[12] & clk_div2[5];
A1L83_p2_out = !clk_div2[10] & !clk_div2[3] & state[2] & !state[1] & clk_div2[4] & clk_div2[7] & clk_div2[6] & clk_div2[11] & !clk_div2[9] & clk_div2[1] & clk_div2[2] & clk_div2[0] & clk_div2[8] & !state[0] & !clk_div2[12] & clk_div2[5];
A1L83_p3_out = clk_div2[10] & clk_div2[3] & state[2] & state[1] & !clk_div2[4] & clk_div2[7] & clk_div2[6] & !clk_div2[11] & clk_div2[9] & !clk_div2[1] & !clk_div2[2] & !clk_div2[0] & clk_div2[8] & !state[0] & !clk_div2[12] & clk_div2[5];
A1L83 = A1L83_p1_out # A1L83_p2_out # A1L83_p3_out;


--A1L93 is Mux~9742 at LC43
A1L93_p1_out = !clk_div2[10] & clk_div2[1] & !clk_div2[2] & !clk_div2[0] & state[1] & !state[2] & clk_div2[9] & clk_div2[3] & clk_div2[7] & clk_div2[11] & clk_div2[8] & clk_div2[4] & !state[0] & !clk_div2[5] & !clk_div2[12] & clk_div2[6];
A1L93_p2_out = clk_div2[10] & clk_div2[1] & clk_div2[2] & !clk_div2[0] & !state[1] & !state[2] & clk_div2[9] & clk_div2[3] & clk_div2[7] & clk_div2[11] & !clk_div2[8] & !clk_div2[4] & !state[0] & clk_div2[5] & !clk_div2[12] & clk_div2[6];
A1L93_p3_out = clk_div2[10] & !clk_div2[1] & !clk_div2[2] & !clk_div2[0] & state[1] & state[2] & clk_div2[9] & clk_div2[3] & clk_div2[7] & !clk_div2[11] & clk_div2[8] & !clk_div2[4] & !state[0] & clk_div2[5] & !clk_div2[12] & clk_div2[6];
A1L93_p4_out = clk_div2[10] & clk_div2[1] & clk_div2[2] & clk_div2[0] & state[1] & state[2] & clk_div2[9] & !clk_div2[3] & !clk_div2[7] & !clk_div2[11] & clk_div2[8] & clk_div2[4] & state[0] & clk_div2[5] & !clk_div2[12] & clk_div2[6];
A1L93 = A1L93_p1_out # A1L93_p2_out # A1L93_p3_out # A1L93_p4_out;


--A1L04 is Mux~9747 at LC39
A1L04_p1_out = !state[0] & clk_div2[10] & state[2] & clk_div2[5] & !clk_div2[2] & !clk_div2[4] & clk_div2[6] & clk_div2[7] & clk_div2[3] & clk_div2[9] & !clk_div2[11] & !clk_div2[1] & state[1] & !clk_div2[0] & !clk_div2[12] & clk_div2[8];
A1L04_p2_out = state[0] & clk_div2[10] & !state[2] & !clk_div2[5] & clk_div2[2] & !clk_div2[4] & clk_div2[6] & !clk_div2[7] & clk_div2[3] & !clk_div2[9] & clk_div2[11] & !clk_div2[1] & !state[1] & clk_div2[0] & !clk_div2[12] & clk_div2[8];
A1L04_p3_out = state[0] & !clk_div2[10] & !state[2] & clk_div2[5] & !clk_div2[2] & clk_div2[4] & !clk_div2[6] & !clk_div2[7] & !clk_div2[3] & clk_div2[9] & clk_div2[11] & !clk_div2[1] & state[1] & clk_div2[0] & !clk_div2[12] & clk_div2[8];
A1L04 = A1L04_p1_out # A1L04_p2_out # A1L04_p3_out;


--A1L12 is Mux~9621sexp1 at SEXP17
A1L12 = EXP(clk_div2[6] & !state[0] & clk_div2[7] & clk_div2[1] & !clk_div2[0] & !clk_div2[5] & clk_div2[4] & clk_div2[11] & clk_div2[8] & !clk_div2[2] & state[1] & clk_div2[3] & !clk_div2[10] & !state[2] & !clk_div2[12] & clk_div2[9]);


--A1L22 is Mux~9621sexp2 at SEXP19
A1L22 = EXP(clk_div2[6] & !state[0] & clk_div2[7] & !clk_div2[1] & !clk_div2[0] & clk_div2[5] & !clk_div2[4] & !clk_div2[11] & clk_div2[8] & !clk_div2[2] & state[1] & clk_div2[3] & clk_div2[10] & state[2] & !clk_div2[12] & clk_div2[9]);


--A1L32 is Mux~9621sexp3 at SEXP22
A1L32 = EXP(clk_div2[6] & !state[0] & clk_div2[7] & clk_div2[1] & !clk_div2[0] & clk_div2[5] & !clk_div2[4] & clk_div2[11] & !clk_div2[8] & clk_div2[2] & !state[1] & clk_div2[3] & clk_div2[10] & !state[2] & !clk_div2[12] & clk_div2[9]);


--A1L42 is Mux~9621sexp4 at SEXP24
A1L42 = EXP(clk_div2[6] & state[0] & !clk_div2[7] & clk_div2[1] & clk_div2[0] & clk_div2[5] & clk_div2[4] & !clk_div2[11] & clk_div2[8] & clk_div2[2] & state[1] & !clk_div2[3] & clk_div2[10] & state[2] & !clk_div2[12] & clk_div2[9]);


--A1L52 is Mux~9621sexp5 at SEXP26
A1L52 = EXP(!clk_div2[6] & state[0] & !clk_div2[7] & !clk_div2[1] & clk_div2[0] & clk_div2[5] & clk_div2[4] & clk_div2[11] & clk_div2[8] & !clk_div2[2] & state[1] & !clk_div2[3] & !clk_div2[10] & !state[2] & !clk_div2[12] & clk_div2[9]);


--A1L62 is Mux~9677sexp4 at SEXP27
A1L62 = EXP(state[2] & !clk_div2[10] & clk_div2[0] & clk_div2[11] & clk_div2[4] & clk_div2[1] & !clk_div2[3] & !clk_div2[9] & !state[0] & !state[1] & clk_div2[5] & clk_div2[8] & clk_div2[2] & clk_div2[7] & clk_div2[6] & !clk_div2[12]);


--A1L72 is Mux~9677sexp5 at SEXP28
A1L72 = EXP(state[2] & !clk_div2[10] & clk_div2[0] & clk_div2[11] & !clk_div2[4] & !clk_div2[1] & !clk_div2[3] & !clk_div2[9] & state[0] & !state[1] & clk_div2[5] & !clk_div2[8] & !clk_div2[2] & clk_div2[7] & clk_div2[6] & !clk_div2[12]);


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--rst is rst at PIN_1
--operation mode is input

rst = INPUT();


--out_bit is out_bit at PIN_12
--operation mode is output

out_bit = OUTPUT(out_bit_tmp);