dial2.map.rpt

CPLD VHDL CODE非常好的参考资料

; lpm_compare.inc                  ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/lpm_compare.inc                      ;
; lpm_counter.inc                  ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/lpm_counter.inc                      ;
; dffeea.inc                       ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/dffeea.inc                           ;
; alt_synch_counter.inc            ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/alt_synch_counter.inc                ;
; alt_synch_counter_f.inc          ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/alt_synch_counter_f.inc              ;
; alt_counter_f10ke.inc            ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.inc                ;
; alt_counter_stratix.inc          ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc              ;
; aglobal50.inc                    ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/aglobal50.inc                        ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+----------------------+-------------------------------------+
; Resource             ; Usage                               ;
+----------------------+-------------------------------------+
; Logic cells          ; 36                                  ;
; Total registers      ; 16                                  ;
; I/O pins             ; 26                                  ;
; Parallel expanders   ; 4                                   ;
; Maximum fan-out node ; lpm_counter:cnt_scan_rtl_0|dffs[13] ;
; Maximum fan-out      ; 18                                  ;
; Total fan-out        ; 252                                 ;
; Average fan-out      ; 4.06                                ;
+----------------------+-------------------------------------+


+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                     ;
+---------------------------------+------------+------+-----------------------------------+
; Compilation Hierarchy Node      ; Macrocells ; Pins ; Full Hierarchy Name               ;
+---------------------------------+------------+------+-----------------------------------+
; |dial2                          ; 36         ; 26   ; |dial2                            ;
;    |lpm_counter:cnt_scan_rtl_0| ; 16         ; 0    ; |dial2|lpm_counter:cnt_scan_rtl_0 ;
+---------------------------------+------------+------+-----------------------------------+


+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_scan_rtl_0 ;
+------------------------+----------+-----------------------------------------+
; Parameter Name         ; Value    ; Type                                    ;
+------------------------+----------+-----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                          ;
; LPM_WIDTH              ; 16       ; Untyped                                 ;
; LPM_DIRECTION          ; UP       ; Untyped                                 ;
; LPM_MODULUS            ; 0        ; Untyped                                 ;
; LPM_AVALUE             ; UNUSED   ; Untyped                                 ;
; LPM_SVALUE             ; UNUSED   ; Untyped                                 ;
; DEVICE_FAMILY          ; MAX7000S ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                      ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                      ;
; CARRY_CNT_EN           ; SMART    ; Untyped                                 ;
; LABWIDE_SCLR           ; ON       ; Untyped                                 ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                                 ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                                 ;
+------------------------+----------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 20 16:01:40 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dial2 -c dial2
Info: Found 2 design units, including 1 entities, in source file dial2.vhd
    Info: Found design unit 1: dial2-arch
    Info: Found entity 1: dial2
Info: Elaborating entity "dial2" for the top level hierarchy
Info: VHDL Case Statement information at dial2.vhd(46): OTHERS choice is never selected
Info: VHDL Case Statement information at dial2.vhd(101): OTHERS choice is never selected
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: "cnt_scan[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[0]" stuck at VCC
    Warning: Pin "dataout[1]" stuck at VCC
    Warning: Pin "dataout[5]" stuck at GND
    Warning: Pin "dataout[6]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 62 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 16 output pins
    Info: Implemented 36 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Thu Apr 20 16:01:42 2006
    Info: Elapsed time: 00:00:02