dial2.tan.rpt

CPLD VHDL CODE非常好的参考资料

+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 16.000 ns       ; datain[7] ; dataout[7] ;
; N/A   ; None              ; 16.000 ns       ; datain[6] ; dataout[7] ;
; N/A   ; None              ; 16.000 ns       ; datain[5] ; dataout[7] ;
; N/A   ; None              ; 16.000 ns       ; datain[7] ; dataout[4] ;
; N/A   ; None              ; 16.000 ns       ; datain[6] ; dataout[4] ;
; N/A   ; None              ; 16.000 ns       ; datain[5] ; dataout[4] ;
; N/A   ; None              ; 16.000 ns       ; datain[7] ; dataout[2] ;
; N/A   ; None              ; 16.000 ns       ; datain[6] ; dataout[2] ;
; N/A   ; None              ; 16.000 ns       ; datain[5] ; dataout[2] ;
; N/A   ; None              ; 16.000 ns       ; datain[7] ; dataout[3] ;
; N/A   ; None              ; 16.000 ns       ; datain[6] ; dataout[3] ;
; N/A   ; None              ; 16.000 ns       ; datain[5] ; dataout[3] ;
; N/A   ; None              ; 15.000 ns       ; datain[0] ; dataout[7] ;
; N/A   ; None              ; 15.000 ns       ; datain[4] ; dataout[7] ;
; N/A   ; None              ; 15.000 ns       ; datain[3] ; dataout[7] ;
; N/A   ; None              ; 15.000 ns       ; datain[2] ; dataout[7] ;
; N/A   ; None              ; 15.000 ns       ; datain[1] ; dataout[7] ;
; N/A   ; None              ; 15.000 ns       ; datain[0] ; dataout[4] ;
; N/A   ; None              ; 15.000 ns       ; datain[4] ; dataout[4] ;
; N/A   ; None              ; 15.000 ns       ; datain[3] ; dataout[4] ;
; N/A   ; None              ; 15.000 ns       ; datain[2] ; dataout[4] ;
; N/A   ; None              ; 15.000 ns       ; datain[1] ; dataout[4] ;
; N/A   ; None              ; 15.000 ns       ; datain[0] ; dataout[2] ;
; N/A   ; None              ; 15.000 ns       ; datain[4] ; dataout[2] ;
; N/A   ; None              ; 15.000 ns       ; datain[3] ; dataout[2] ;
; N/A   ; None              ; 15.000 ns       ; datain[2] ; dataout[2] ;
; N/A   ; None              ; 15.000 ns       ; datain[1] ; dataout[2] ;
; N/A   ; None              ; 15.000 ns       ; datain[0] ; dataout[3] ;
; N/A   ; None              ; 15.000 ns       ; datain[4] ; dataout[3] ;
; N/A   ; None              ; 15.000 ns       ; datain[3] ; dataout[3] ;
; N/A   ; None              ; 15.000 ns       ; datain[2] ; dataout[3] ;
; N/A   ; None              ; 15.000 ns       ; datain[1] ; dataout[3] ;
+-------+-------------------+-----------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 20 16:01:47 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dial2 -c dial2
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "lpm_counter:cnt_scan_rtl_0|dffs[0]" and destination register "lpm_counter:cnt_scan_rtl_0|dffs[15]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC102; Fanout = 41; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[15]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC102; Fanout = 41; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[15]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "dataout[7]" through register "lpm_counter:cnt_scan_rtl_0|dffs[13]" is 18.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC98; Fanout = 43; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[13]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 14.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC98; Fanout = 43; REG Node = 'lpm_counter:cnt_scan_rtl_0|dffs[13]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC87; Fanout = 1; COMB Node = 'data4[0]~141'
        Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC88; Fanout = 1; COMB Node = 'data4[0]~128'
        Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 14.000 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dataout[7]'
        Info: Total cell delay = 12.000 ns ( 85.71 % )
        Info: Total interconnect delay = 2.000 ns ( 14.29 % )
Info: Longest tpd from source pin "datain[7]" to destination pin "dataout[7]" is 16.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 4; PIN Node = 'datain[7]'
    Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC87; Fanout = 1; COMB Node = 'data4[0]~141'
    Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC88; Fanout = 1; COMB Node = 'data4[0]~128'
    Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 16.000 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dataout[7]'
    Info: Total cell delay = 14.000 ns ( 87.50 % )
    Info: Total interconnect delay = 2.000 ns ( 12.50 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Apr 20 16:01:48 2006
    Info: Elapsed time: 00:00:01