serial.fit.eqn

CPLD VHDL CODE非常好的参考资料

rxd_reg1_reg_input = rxd_reg1_or_out;
rxd_reg1 = DFFE(rxd_reg1_reg_input, clkbaud8x, GLOBAL(rst), , );


--cnt_delay[19] is cnt_delay[19] at LC13
cnt_delay[19]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & !cnt_delay[17] & !cnt_delay[16] & cnt_delay[19] & cnt_delay[18];
cnt_delay[19]_p2_out = cnt_delay[4] & cnt_delay[5] & cnt_delay[0] & cnt_delay[7] & cnt_delay[15] & cnt_delay[9] & cnt_delay[1] & cnt_delay[6] & cnt_delay[14] & cnt_delay[2] & cnt_delay[3] & cnt_delay[11] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & cnt_delay[17] & cnt_delay[16] & cnt_delay[18];
cnt_delay[19]_or_out = cnt_delay[19]_p1_out # cnt_delay[19]_p2_out;
cnt_delay[19]_reg_input = cnt_delay[19]_or_out;
cnt_delay[19] = TFFE(cnt_delay[19]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--rxd_reg2 is rxd_reg2 at LC113
rxd_reg2_or_out = rxd_reg1;
rxd_reg2_reg_input = rxd_reg2_or_out;
rxd_reg2 = DFFE(rxd_reg2_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_rec[1] is state_rec[1] at LC124
state_rec[1]_p1_out = state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & !state_rec[3];
state_rec[1]_or_out = state_rec[1]_p1_out;
state_rec[1]_reg_input = state_rec[1]_or_out;
state_rec[1] = TFFE(state_rec[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--start_delaycnt is start_delaycnt at LC3
start_delaycnt_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & !cnt_delay[13] & !cnt_delay[10] & !cnt_delay[12] & !cnt_delay[19] & !cnt_delay[18] & !key_input & !cnt_delay[8] & !start_delaycnt;
start_delaycnt_p2_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[13] & cnt_delay[10] & cnt_delay[12] & cnt_delay[19] & cnt_delay[18] & cnt_delay[8] & start_delaycnt;
start_delaycnt_or_out = start_delaycnt_p1_out # start_delaycnt_p2_out;
start_delaycnt_reg_input = start_delaycnt_or_out;
start_delaycnt = TFFE(start_delaycnt_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--state_tras[3] is state_tras[3] at LC59
state_tras[3]_p1_out = state_tras[2] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[0] & key_entry2;
state_tras[3]_or_out = state_tras[3]_p1_out;
state_tras[3]_reg_input = state_tras[3]_or_out;
state_tras[3] = TFFE(state_tras[3]_reg_input, clkbaud8x, GLOBAL(rst), , );


--cnt_delay[0] is cnt_delay[0] at LC4
cnt_delay[0]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & cnt_delay[18] & !cnt_delay[0];
cnt_delay[0]_or_out = cnt_delay[0]_p1_out;
cnt_delay[0]_reg_input = !cnt_delay[0]_or_out;
cnt_delay[0] = TFFE(cnt_delay[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--cnt_delay[1] is cnt_delay[1] at LC41
cnt_delay[1]_or_out = cnt_delay[0];
cnt_delay[1]_reg_input = cnt_delay[1]_or_out;
cnt_delay[1] = TFFE(cnt_delay[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--recstart_tmp is recstart_tmp at LC123
recstart_tmp_p1_out = rxd_reg2 & !rxd_reg1 & !state_rec[3] & !state_rec[0] & !state_rec[2] & !state_rec[1];
recstart_tmp_p2_out = !state_rec[3] & !state_rec[0] & !state_rec[2] & !state_rec[1] & recstart_tmp;
recstart_tmp_or_out = recstart_tmp_p1_out # recstart_tmp_p2_out;
recstart_tmp_reg_input = recstart_tmp_or_out;
recstart_tmp = TFFE(recstart_tmp_reg_input, clkbaud8x, GLOBAL(rst), , );


--send_state[0] is send_state[0] at LC35
send_state[0]_p1_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & state_tras[2] & key_entry2 & state_tras[0] & state_tras[1];
send_state[0]_or_out = send_state[0]_p1_out;
send_state[0]_reg_input = send_state[0]_or_out;
send_state[0] = TFFE(send_state[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--cnt_delay[2] is cnt_delay[2] at LC44
cnt_delay[2]_p1_out = cnt_delay[1] & cnt_delay[0];
cnt_delay[2]_or_out = cnt_delay[2]_p1_out;
cnt_delay[2]_reg_input = cnt_delay[2]_or_out;
cnt_delay[2] = TFFE(cnt_delay[2]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--recstart is recstart at LC121
recstart_p1_out = !state_rec[0] & recstart_tmp & !state_rec[3] & !state_rec[2] & !state_rec[1] & !recstart;
recstart_p2_out = state_rec[0] & state_rec[3] & !state_rec[2] & !state_rec[1] & recstart & div8_rec_reg[1] & div8_rec_reg[0] & div8_rec_reg[2];
recstart_or_out = recstart_p1_out # recstart_p2_out;
recstart_reg_input = recstart_or_out;
recstart = TFFE(recstart_reg_input, clkbaud8x, GLOBAL(rst), , );


--cnt_delay[3] is cnt_delay[3] at LC45
cnt_delay[3]_p1_out = cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[3]_or_out = cnt_delay[3]_p1_out;
cnt_delay[3]_reg_input = cnt_delay[3]_or_out;
cnt_delay[3] = TFFE(cnt_delay[3]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--send_state[1] is send_state[1] at LC60
send_state[1]_p1_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & send_state[0] & state_tras[3] & state_tras[2] & key_entry2 & state_tras[0] & state_tras[1];
send_state[1]_or_out = send_state[1]_p1_out;
send_state[1]_reg_input = send_state[1]_or_out;
send_state[1] = TFFE(send_state[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_rec_reg[0] is div8_rec_reg[0] at LC120
div8_rec_reg[0]_or_out = recstart;
div8_rec_reg[0]_reg_input = div8_rec_reg[0]_or_out;
div8_rec_reg[0] = TFFE(div8_rec_reg[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--cnt_delay[4] is cnt_delay[4] at LC46
cnt_delay[4]_p1_out = cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[4]_or_out = cnt_delay[4]_p1_out;
cnt_delay[4]_reg_input = cnt_delay[4]_or_out;
cnt_delay[4] = TFFE(cnt_delay[4]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div8_rec_reg[1] is div8_rec_reg[1] at LC116
div8_rec_reg[1]_p1_out = div8_rec_reg[0] & recstart;
div8_rec_reg[1]_or_out = div8_rec_reg[1]_p1_out;
div8_rec_reg[1]_reg_input = div8_rec_reg[1]_or_out;
div8_rec_reg[1] = TFFE(div8_rec_reg[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--send_state[2] is send_state[2] at LC61
send_state[2]_p1_out = send_state[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & send_state[0] & state_tras[3] & state_tras[2] & key_entry2 & state_tras[0] & state_tras[1];
send_state[2]_or_out = send_state[2]_p1_out;
send_state[2]_reg_input = send_state[2]_or_out;
send_state[2] = TFFE(send_state[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_rec_reg[2] is div8_rec_reg[2] at LC114
div8_rec_reg[2]_p1_out = div8_rec_reg[1] & div8_rec_reg[0] & recstart;
div8_rec_reg[2]_or_out = div8_rec_reg[2]_p1_out;
div8_rec_reg[2]_reg_input = div8_rec_reg[2]_or_out;
div8_rec_reg[2] = TFFE(div8_rec_reg[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--key_entry1 is key_entry1 at LC1
key_entry1_p1_out = !key_entry2 & key_entry1;
key_entry1_p2_out = !key_entry2 & !key_input & !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & cnt_delay[18];
key_entry1_or_out = key_entry1_p1_out # key_entry1_p2_out;
key_entry1_reg_input = key_entry1_or_out;
key_entry1 = DFFE(key_entry1_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--key_entry2 is key_entry2 at LC58
key_entry2_p1_out = !key_entry1 & !key_entry2;
key_entry2_p2_out = key_entry2 & send_state[0] & send_state[2] & send_state[1] & !state_tras[3] & !state_tras[0] & !state_tras[1] & !state_tras[2];
key_entry2_or_out = key_entry2_p1_out # key_entry2_p2_out;
key_entry2_reg_input = !(key_entry2_or_out);
key_entry2 = DFFE(key_entry2_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_rec[2] is state_rec[2] at LC128
state_rec[2]_p1_out = state_rec[1] & state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & !state_rec[3];
state_rec[2]_or_out = state_rec[2]_p1_out;
state_rec[2]_reg_input = state_rec[2]_or_out;
state_rec[2] = TFFE(state_rec[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_tras[2] is state_tras[2] at LC40
state_tras[2]_p1_out = state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[0] & key_entry2;
state_tras[2]_or_out = state_tras[2]_p1_out;
state_tras[2]_reg_input = state_tras[2]_or_out;
state_tras[2] = TFFE(state_tras[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_rec[3] is state_rec[3] at LC119
state_rec[3]_p1_out = state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & state_rec[2] & state_rec[1] & !state_rec[3];
state_rec[3]_p2_out = state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & !state_rec[2] & !state_rec[1] & state_rec[3];
state_rec[3]_or_out = state_rec[3]_p1_out # state_rec[3]_p2_out;
state_rec[3]_reg_input = state_rec[3]_or_out;
state_rec[3] = TFFE(state_rec[3]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L19 is rxd_buf~433 at LC122
A1L19_p1_out = !state_rec[3] & state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1];
A1L19_p2_out = !state_rec[3] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & state_rec[2];
A1L19_p3_out = !state_rec[3] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & state_rec[1];
A1L19_p4_out = state_rec[3] & !state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1] & !state_rec[2] & !state_rec[1];
A1L19_or_out = A1L19_p1_out # A1L19_p2_out # A1L19_p3_out # A1L19_p4_out;
A1L19 = A1L19_or_out;


--rxd_buf[7] is rxd_buf[7] at LC95
rxd_buf[7]_p1_out = rxd_reg2 & A1L19;
rxd_buf[7]_p2_out = !A1L19 & rxd_buf[7];
rxd_buf[7]_or_out = rxd_buf[7]_p1_out # rxd_buf[7]_p2_out;
rxd_buf[7]_reg_input = rxd_buf[7]_or_out;
rxd_buf[7] = DFFE(rxd_buf[7]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L821 is trasstart~49 at SEXP37
A1L821 = EXP(state_tras[2] & state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2);


--A1L031 is trasstart~51 at SEXP36
A1L031 = EXP(state_tras[0] & state_tras[1]);


--trasstart is trasstart at LC48
trasstart_p0_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & state_tras[2] & key_entry2 & A1L031;
trasstart_p1_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & state_tras[1] & !state_tras[2] & key_entry2;
trasstart_p2_out = A1L821 & trasstart;
trasstart_p4_out = !state_tras[3] & !state_tras[1] & !state_tras[2] & key_entry2 & A1L921 & !state_tras[0];
trasstart_or_out = trasstart_p0_out # trasstart_p1_out # trasstart_p2_out # trasstart_p4_out;
trasstart_reg_input = trasstart_or_out;
trasstart = DFFE(trasstart_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_tras_reg[0] is div8_tras_reg[0] at LC38
div8_tras_reg[0]_or_out = trasstart;
div8_tras_reg[0]_reg_input = div8_tras_reg[0]_or_out;
div8_tras_reg[0] = TFFE(div8_tras_reg[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_buf[6] is rxd_buf[6] at LC92
rxd_buf[6]_p1_out = rxd_buf[7] & A1L19;
rxd_buf[6]_p2_out = !A1L19 & rxd_buf[6];
rxd_buf[6]_or_out = rxd_buf[6]_p1_out # rxd_buf[6]_p2_out;
rxd_buf[6]_reg_input = rxd_buf[6]_or_out;
rxd_buf[6] = DFFE(rxd_buf[6]_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_tras_reg[1] is div8_tras_reg[1] at LC36
div8_tras_reg[1]_p1_out = div8_tras_reg[0] & trasstart;
div8_tras_reg[1]_or_out = div8_tras_reg[1]_p1_out;
div8_tras_reg[1]_reg_input = div8_tras_reg[1]_or_out;
div8_tras_reg[1] = TFFE(div8_tras_reg[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_buf[5] is rxd_buf[5] at LC90
rxd_buf[5]_p1_out = rxd_buf[6] & A1L19;
rxd_buf[5]_p2_out = !A1L19 & rxd_buf[5];
rxd_buf[5]_or_out = rxd_buf[5]_p1_out # rxd_buf[5]_p2_out;
rxd_buf[5]_reg_input = rxd_buf[5]_or_out;
rxd_buf[5] = DFFE(rxd_buf[5]_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_tras_reg[2] is div8_tras_reg[2] at LC33
div8_tras_reg[2]_p1_out = div8_tras_reg[1] & div8_tras_reg[0] & trasstart;
div8_tras_reg[2]_or_out = div8_tras_reg[2]_p1_out;
div8_tras_reg[2]_reg_input = div8_tras_reg[2]_or_out;
div8_tras_reg[2] = TFFE(div8_tras_reg[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_buf[4] is rxd_buf[4] at LC89
rxd_buf[4]_p1_out = rxd_buf[5] & A1L19;
rxd_buf[4]_p2_out = !A1L19 & rxd_buf[4];
rxd_buf[4]_or_out = rxd_buf[4]_p1_out # rxd_buf[4]_p2_out;
rxd_buf[4]_reg_input = rxd_buf[4]_or_out;
rxd_buf[4] = DFFE(rxd_buf[4]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_buf[3] is rxd_buf[3] at LC84
rxd_buf[3]_p1_out = rxd_buf[4] & A1L19;
rxd_buf[3]_p2_out = !A1L19 & rxd_buf[3];
rxd_buf[3]_or_out = rxd_buf[3]_p1_out # rxd_buf[3]_p2_out;
rxd_buf[3]_reg_input = rxd_buf[3]_or_out;
rxd_buf[3] = DFFE(rxd_buf[3]_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_tras[1] is state_tras[1] at LC34
state_tras[1]_p1_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[0] & key_entry2;
state_tras[1]_or_out = state_tras[1]_p1_out;
state_tras[1]_reg_input = state_tras[1]_or_out;
state_tras[1] = TFFE(state_tras[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_buf[2] is rxd_buf[2] at LC82
rxd_buf[2]_p1_out = rxd_buf[3] & A1L19;
rxd_buf[2]_p2_out = !A1L19 & rxd_buf[2];
rxd_buf[2]_or_out = rxd_buf[2]_p1_out # rxd_buf[2]_p2_out;
rxd_buf[2]_reg_input = rxd_buf[2]_or_out;
rxd_buf[2] = DFFE(rxd_buf[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_buf[1] is rxd_buf[1] at LC83
rxd_buf[1]_p1_out = rxd_buf[2] & A1L19;
rxd_buf[1]_p2_out = !A1L19 & rxd_buf[1];
rxd_buf[1]_or_out = rxd_buf[1]_p1_out # rxd_buf[1]_p2_out;
rxd_buf[1]_reg_input = rxd_buf[1]_or_out;
rxd_buf[1] = DFFE(rxd_buf[1]_reg_input, clkbaud8x, GLOBAL(rst), , );