serial.fit.eqn

CPLD VHDL CODE非常好的参考资料

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--div_reg[0] is div_reg[0] at LC62
div_reg[0]_reg_input = VCC;
div_reg[0] = TFFE(div_reg[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[5] is cnt_delay[5] at LC47
cnt_delay[5]_p1_out = cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[5]_or_out = cnt_delay[5]_p1_out;
cnt_delay[5]_reg_input = cnt_delay[5]_or_out;
cnt_delay[5] = TFFE(cnt_delay[5]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[1] is div_reg[1] at LC64
div_reg[1]_or_out = div_reg[0];
div_reg[1]_reg_input = div_reg[1]_or_out;
div_reg[1] = TFFE(div_reg[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[6] is cnt_delay[6] at LC39
cnt_delay[6]_p1_out = cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[6]_or_out = cnt_delay[6]_p1_out;
cnt_delay[6]_reg_input = cnt_delay[6]_or_out;
cnt_delay[6] = TFFE(cnt_delay[6]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[2] is div_reg[2] at LC31
div_reg[2]_p1_out = !div_reg[13] & !div_reg[15] & !div_reg[12] & div_reg[8] & !div_reg[3] & !div_reg[10] & !div_reg[4] & !div_reg[5] & !div_reg[9] & !div_reg[6] & !div_reg[7] & !div_reg[11] & !div_reg[14] & !div_reg[2];
div_reg[2]_p2_out = div_reg[2] & div_reg[1] & div_reg[0];
div_reg[2]_p3_out = !div_reg[2] & !div_reg[1];
div_reg[2]_p4_out = !div_reg[2] & !div_reg[0];
div_reg[2]_or_out = div_reg[2]_p1_out # div_reg[2]_p2_out # div_reg[2]_p3_out # div_reg[2]_p4_out;
div_reg[2]_reg_input = !(div_reg[2]_or_out);
div_reg[2] = DFFE(div_reg[2]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[7] is cnt_delay[7] at LC16
cnt_delay[7]_p1_out = cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[7]_or_out = cnt_delay[7]_p1_out;
cnt_delay[7]_reg_input = cnt_delay[7]_or_out;
cnt_delay[7] = TFFE(cnt_delay[7]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[3] is div_reg[3] at LC32
div_reg[3]_p1_out = div_reg[2] & div_reg[1] & div_reg[0];
div_reg[3]_or_out = div_reg[3]_p1_out;
div_reg[3]_reg_input = div_reg[3]_or_out;
div_reg[3] = TFFE(div_reg[3]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--div_reg[4] is div_reg[4] at LC18
div_reg[4]_p1_out = div_reg[3] & div_reg[2] & div_reg[1] & div_reg[0];
div_reg[4]_or_out = div_reg[4]_p1_out;
div_reg[4]_reg_input = div_reg[4]_or_out;
div_reg[4] = TFFE(div_reg[4]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[8] is cnt_delay[8] at LC2
cnt_delay[8]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[18] & cnt_delay[8];
cnt_delay[8]_p2_out = cnt_delay[4] & cnt_delay[5] & cnt_delay[0] & cnt_delay[7] & cnt_delay[1] & cnt_delay[6] & cnt_delay[2] & cnt_delay[3];
cnt_delay[8]_or_out = cnt_delay[8]_p1_out # cnt_delay[8]_p2_out;
cnt_delay[8]_reg_input = cnt_delay[8]_or_out;
cnt_delay[8] = TFFE(cnt_delay[8]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[5] is div_reg[5] at LC19
div_reg[5]_p1_out = div_reg[4] & div_reg[3] & div_reg[2] & div_reg[1] & div_reg[0];
div_reg[5]_or_out = div_reg[5]_p1_out;
div_reg[5]_reg_input = div_reg[5]_or_out;
div_reg[5] = TFFE(div_reg[5]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[9] is cnt_delay[9] at LC5
cnt_delay[9]_p1_out = cnt_delay[8] & cnt_delay[3] & cnt_delay[2] & cnt_delay[7] & cnt_delay[6] & cnt_delay[1] & cnt_delay[0] & cnt_delay[5] & cnt_delay[4];
cnt_delay[9]_or_out = cnt_delay[9]_p1_out;
cnt_delay[9]_reg_input = cnt_delay[9]_or_out;
cnt_delay[9] = TFFE(cnt_delay[9]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[6] is div_reg[6] at LC24
div_reg[6]_p1_out = div_reg[5] & div_reg[4] & div_reg[3] & div_reg[2] & div_reg[1] & div_reg[0];
div_reg[6]_or_out = div_reg[6]_p1_out;
div_reg[6]_reg_input = div_reg[6]_or_out;
div_reg[6] = TFFE(div_reg[6]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[10] is cnt_delay[10] at LC10
cnt_delay[10]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[13] & cnt_delay[12] & cnt_delay[18] & !cnt_delay[9] & cnt_delay[8] & cnt_delay[10];
cnt_delay[10]_p2_out = cnt_delay[4] & cnt_delay[5] & cnt_delay[0] & cnt_delay[7] & cnt_delay[1] & cnt_delay[6] & cnt_delay[2] & cnt_delay[3] & cnt_delay[9] & cnt_delay[8];
cnt_delay[10]_or_out = cnt_delay[10]_p1_out # cnt_delay[10]_p2_out;
cnt_delay[10]_reg_input = cnt_delay[10]_or_out;
cnt_delay[10] = TFFE(cnt_delay[10]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[7] is div_reg[7] at LC20
div_reg[7]_p1_out = div_reg[6] & div_reg[5] & div_reg[4] & div_reg[3] & div_reg[2] & div_reg[1] & div_reg[0];
div_reg[7]_or_out = div_reg[7]_p1_out;
div_reg[7]_reg_input = div_reg[7]_or_out;
div_reg[7] = TFFE(div_reg[7]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[11] is cnt_delay[11] at LC7
cnt_delay[11]_p1_out = cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[3] & cnt_delay[2] & cnt_delay[7] & cnt_delay[6] & cnt_delay[1] & cnt_delay[0] & cnt_delay[5] & cnt_delay[4];
cnt_delay[11]_or_out = cnt_delay[11]_p1_out;
cnt_delay[11]_reg_input = cnt_delay[11]_or_out;
cnt_delay[11] = TFFE(cnt_delay[11]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--C3L1 is lpm_add_sub:add_rtl_0|addcore:adder[1]|unreg_result[0]~21 at LC22
C3L1_p1_out = div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
C3L1_or_out = !div_reg[8];
C3L1 = C3L1_p1_out $ C3L1_or_out;


--div_reg[8] is div_reg[8] at LC25
div_reg[8]_p1_out = !C3L1 & A1L46;
div_reg[8]_or_out = div_reg[8]_p1_out;
div_reg[8]_reg_input = div_reg[8]_or_out;
div_reg[8] = DFFE(div_reg[8]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[12] is cnt_delay[12] at LC11
cnt_delay[12]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & cnt_delay[19] & cnt_delay[13] & cnt_delay[18] & !cnt_delay[9] & cnt_delay[10] & !cnt_delay[11] & cnt_delay[8] & cnt_delay[12];
cnt_delay[12]_p2_out = cnt_delay[4] & cnt_delay[5] & cnt_delay[0] & cnt_delay[7] & cnt_delay[1] & cnt_delay[6] & cnt_delay[2] & cnt_delay[3] & cnt_delay[9] & cnt_delay[10] & cnt_delay[11] & cnt_delay[8];
cnt_delay[12]_or_out = cnt_delay[12]_p1_out # cnt_delay[12]_p2_out;
cnt_delay[12]_reg_input = cnt_delay[12]_or_out;
cnt_delay[12] = TFFE(cnt_delay[12]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[9] is div_reg[9] at LC28
div_reg[9]_p1_out = div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[9]_or_out = div_reg[9]_p1_out;
div_reg[9]_reg_input = div_reg[9]_or_out;
div_reg[9] = TFFE(div_reg[9]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[13] is cnt_delay[13] at LC15
cnt_delay[13]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & cnt_delay[19] & cnt_delay[18] & !cnt_delay[9] & cnt_delay[10] & !cnt_delay[11] & cnt_delay[12] & cnt_delay[8] & cnt_delay[13];
cnt_delay[13]_p2_out = cnt_delay[4] & cnt_delay[5] & cnt_delay[0] & cnt_delay[7] & cnt_delay[1] & cnt_delay[6] & cnt_delay[2] & cnt_delay[3] & cnt_delay[9] & cnt_delay[10] & cnt_delay[11] & cnt_delay[12] & cnt_delay[8];
cnt_delay[13]_or_out = cnt_delay[13]_p1_out # cnt_delay[13]_p2_out;
cnt_delay[13]_reg_input = cnt_delay[13]_or_out;
cnt_delay[13] = TFFE(cnt_delay[13]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[10] is div_reg[10] at LC30
div_reg[10]_p1_out = div_reg[9] & div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[10]_or_out = div_reg[10]_p1_out;
div_reg[10]_reg_input = div_reg[10]_or_out;
div_reg[10] = TFFE(div_reg[10]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[14] is cnt_delay[14] at LC14
cnt_delay[14]_p1_out = cnt_delay[13] & cnt_delay[12] & cnt_delay[11] & cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[3] & cnt_delay[2] & cnt_delay[7] & cnt_delay[6] & cnt_delay[1] & cnt_delay[0] & cnt_delay[5] & cnt_delay[4];
cnt_delay[14]_or_out = cnt_delay[14]_p1_out;
cnt_delay[14]_reg_input = cnt_delay[14]_or_out;
cnt_delay[14] = TFFE(cnt_delay[14]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[11] is div_reg[11] at LC29
div_reg[11]_p1_out = div_reg[10] & div_reg[9] & div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[11]_or_out = div_reg[11]_p1_out;
div_reg[11]_reg_input = div_reg[11]_or_out;
div_reg[11] = TFFE(div_reg[11]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[15] is cnt_delay[15] at LC12
cnt_delay[15]_p1_out = cnt_delay[14] & cnt_delay[13] & cnt_delay[12] & cnt_delay[11] & cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[3] & cnt_delay[2] & cnt_delay[7] & cnt_delay[6] & cnt_delay[1] & cnt_delay[0] & cnt_delay[5] & cnt_delay[4];
cnt_delay[15]_or_out = cnt_delay[15]_p1_out;
cnt_delay[15]_reg_input = cnt_delay[15]_or_out;
cnt_delay[15] = TFFE(cnt_delay[15]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[12] is div_reg[12] at LC27
div_reg[12]_p1_out = div_reg[11] & div_reg[10] & div_reg[9] & div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[12]_or_out = div_reg[12]_p1_out;
div_reg[12]_reg_input = div_reg[12]_or_out;
div_reg[12] = TFFE(div_reg[12]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--div_reg[13] is div_reg[13] at LC26
div_reg[13]_p1_out = div_reg[12] & div_reg[11] & div_reg[10] & div_reg[9] & div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[13]_or_out = div_reg[13]_p1_out;
div_reg[13]_reg_input = div_reg[13]_or_out;
div_reg[13] = TFFE(div_reg[13]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[16] is cnt_delay[16] at LC9
cnt_delay[16]_p1_out = cnt_delay[3] & cnt_delay[2] & cnt_delay[7] & cnt_delay[6] & cnt_delay[1] & cnt_delay[0] & cnt_delay[5] & cnt_delay[4] & cnt_delay[10] & cnt_delay[11] & cnt_delay[15] & cnt_delay[14] & cnt_delay[8] & cnt_delay[9] & cnt_delay[13] & cnt_delay[12];
cnt_delay[16]_or_out = cnt_delay[16]_p1_out;
cnt_delay[16]_reg_input = cnt_delay[16]_or_out;
cnt_delay[16] = TFFE(cnt_delay[16]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[14] is div_reg[14] at LC23
div_reg[14]_p1_out = div_reg[13] & div_reg[12] & div_reg[11] & div_reg[10] & div_reg[9] & div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[14]_or_out = div_reg[14]_p1_out;
div_reg[14]_reg_input = div_reg[14]_or_out;
div_reg[14] = TFFE(div_reg[14]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[17] is cnt_delay[17] at LC8
cnt_delay[17]_p1_out = cnt_delay[16] & cnt_delay[3] & cnt_delay[2] & cnt_delay[7] & cnt_delay[6] & cnt_delay[1] & cnt_delay[0] & cnt_delay[5] & cnt_delay[4] & cnt_delay[10] & cnt_delay[11] & cnt_delay[15] & cnt_delay[14] & cnt_delay[8] & cnt_delay[9] & cnt_delay[13] & cnt_delay[12];
cnt_delay[17]_or_out = cnt_delay[17]_p1_out;
cnt_delay[17]_reg_input = cnt_delay[17]_or_out;
cnt_delay[17] = TFFE(cnt_delay[17]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--div_reg[15] is div_reg[15] at LC21
div_reg[15]_p1_out = div_reg[14] & div_reg[13] & div_reg[12] & div_reg[11] & div_reg[10] & div_reg[9] & div_reg[8] & div_reg[3] & div_reg[2] & div_reg[7] & div_reg[6] & div_reg[1] & div_reg[0] & div_reg[5] & div_reg[4];
div_reg[15]_or_out = div_reg[15]_p1_out;
div_reg[15]_reg_input = div_reg[15]_or_out;
div_reg[15] = TFFE(div_reg[15]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[18] is cnt_delay[18] at LC6
cnt_delay[18]_p1_out = !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & !cnt_delay[17] & !cnt_delay[16] & cnt_delay[18];
cnt_delay[18]_p2_out = cnt_delay[4] & cnt_delay[5] & cnt_delay[0] & cnt_delay[7] & cnt_delay[15] & cnt_delay[9] & cnt_delay[1] & cnt_delay[6] & cnt_delay[14] & cnt_delay[2] & cnt_delay[3] & cnt_delay[11] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & cnt_delay[17] & cnt_delay[16];
cnt_delay[18]_or_out = cnt_delay[18]_p1_out # cnt_delay[18]_p2_out;
cnt_delay[18]_reg_input = cnt_delay[18]_or_out;
cnt_delay[18] = TFFE(cnt_delay[18]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--clkbaud8x is clkbaud8x at LC17
clkbaud8x_p1_out = div_reg[1] & div_reg[0] & !div_reg[13] & !div_reg[15] & !div_reg[12] & div_reg[8] & !div_reg[3] & !div_reg[10] & !div_reg[4] & !div_reg[5] & !div_reg[2] & !div_reg[9] & !div_reg[6] & !div_reg[7] & !div_reg[11] & !div_reg[14];
clkbaud8x_or_out = clkbaud8x_p1_out;
clkbaud8x_reg_input = clkbaud8x_or_out;
clkbaud8x = TFFE(clkbaud8x_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--state_tras[0] is state_tras[0] at LC75
state_tras[0]_p1_out = key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
state_tras[0]_p2_out = send_state[0] & send_state[2] & send_state[1] & !state_tras[1] & !state_tras[2] & !state_tras[3] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
state_tras[0]_p4_out = !state_tras[1] & !state_tras[2] & !state_tras[3] & key_entry2 & !trasstart & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
state_tras[0]_or_out = state_tras[0] # state_tras[0]_p2_out # state_tras[0]_p4_out;
state_tras[0]_reg_input = state_tras[0]_p1_out $ state_tras[0]_or_out;
state_tras[0] = DFFE(state_tras[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L011 is state_rec[0]~711 at SEXP117
A1L011 = EXP(recstart_tmp & !state_rec[2] & !state_rec[1] & !state_rec[0] & !state_rec[3]);


--A1L111 is state_rec[0]~712 at SEXP116
A1L111 = EXP(!state_rec[2] & !state_rec[1] & state_rec[3] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1]);


--A1L211 is state_rec[0]~713 at SEXP115
A1L211 = EXP(state_rec[2] & !state_rec[3] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1]);


--A1L311 is state_rec[0]~714 at SEXP114
A1L311 = EXP(state_rec[1] & !state_rec[3] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1]);


--A1L411 is state_rec[0]~715 at SEXP113
A1L411 = EXP(!state_rec[2] & !state_rec[1] & state_rec[0] & div8_rec_reg[2] & div8_rec_reg[0] & div8_rec_reg[1]);


--state_rec[0] is state_rec[0] at LC125
state_rec[0]_p1_out = A1L011 & A1L111 & A1L211 & A1L311 & A1L411;
state_rec[0]_or_out = state_rec[0]_p1_out;
state_rec[0]_reg_input = !state_rec[0]_or_out;
state_rec[0] = TFFE(state_rec[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--rxd_reg1 is rxd_reg1 at LC96
rxd_reg1_or_out = rxd;