serial.tan.summary

CPLD VHDL CODE非常好的参考资料

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.000 ns
From           : key_input
To             : key_entry1
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 34.000 ns
From           : rxd_buf[0]
To             : seg_data[2]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.000 ns
From           : rxd
To             : rxd_reg1
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 45.45 MHz ( period = 22.000 ns )
From           : div_reg[4]
To             : div_reg[8]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : key_entry1
To             : txd_buf[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 7

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 7

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