bcd.map.rpt

CPLD VHDL CODE非常好的参考资料

; a_csnbuffer.inc                  ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.inc                  ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction    ; d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf                  ;
; look_add.tdf                     ; yes             ; Megafunction    ; d:/altera/quartus50/libraries/megafunctions/look_add.tdf                     ;
; altshift.tdf                     ; yes             ; Megafunction    ; d:/altera/quartus50/libraries/megafunctions/altshift.tdf                     ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 33                   ;
; Total registers      ; 22                   ;
; I/O pins             ; 16                   ;
; Parallel expanders   ; 3                    ;
; Maximum fan-out node ; clk                  ;
; Maximum fan-out      ; 22                   ;
; Total fan-out        ; 367                  ;
; Average fan-out      ; 7.49                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |bcd                       ; 33         ; 16   ; |bcd                ;
+----------------------------+------------+------+---------------------+


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 20          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_5ph ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/基础实验/二进制转BCD码/bcd.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Dec 13 17:32:09 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bcd -c bcd
Info: Found 2 design units, including 1 entities, in source file bcd.vhd
    Info: Found design unit 1: bcd-arch
    Info: Found entity 1: bcd
Info: Elaborating entity "bcd" for the top level hierarchy
Warning: VHDL Process Statement warning at bcd.vhd(56): signal "code_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bcd.vhd(58): signal "code_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at bcd.vhd(84): OTHERS choice is never selected
Info: VHDL Case Statement information at bcd.vhd(126): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 20 buffer(s)
    Info: Ignored 20 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "c[0]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 49 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 10 output pins
    Info: Implemented 33 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue Dec 13 17:32:14 2005
    Info: Elapsed time: 00:00:06