bcd.tan.rpt

CPLD VHDL CODE非常好的参考资料

; N/A   ; None              ; 16.000 ns       ; a[3] ; c[4] ;
; N/A   ; None              ; 16.000 ns       ; a[1] ; c[4] ;
; N/A   ; None              ; 16.000 ns       ; a[0] ; c[7] ;
; N/A   ; None              ; 16.000 ns       ; a[2] ; c[7] ;
; N/A   ; None              ; 16.000 ns       ; a[3] ; c[7] ;
; N/A   ; None              ; 16.000 ns       ; a[1] ; c[7] ;
; N/A   ; None              ; 15.000 ns       ; a[0] ; c[3] ;
; N/A   ; None              ; 15.000 ns       ; a[2] ; c[3] ;
; N/A   ; None              ; 15.000 ns       ; a[3] ; c[3] ;
; N/A   ; None              ; 15.000 ns       ; a[1] ; c[3] ;
; N/A   ; None              ; 15.000 ns       ; a[0] ; c[6] ;
; N/A   ; None              ; 15.000 ns       ; a[2] ; c[6] ;
; N/A   ; None              ; 15.000 ns       ; a[3] ; c[6] ;
; N/A   ; None              ; 15.000 ns       ; a[1] ; c[6] ;
; N/A   ; None              ; 15.000 ns       ; a[0] ; c[1] ;
; N/A   ; None              ; 15.000 ns       ; a[2] ; c[1] ;
; N/A   ; None              ; 15.000 ns       ; a[3] ; c[1] ;
; N/A   ; None              ; 15.000 ns       ; a[1] ; c[1] ;
; N/A   ; None              ; 15.000 ns       ; a[0] ; c[5] ;
; N/A   ; None              ; 15.000 ns       ; a[2] ; c[5] ;
; N/A   ; None              ; 15.000 ns       ; a[3] ; c[5] ;
; N/A   ; None              ; 15.000 ns       ; a[1] ; c[5] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Dec 13 17:32:23 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcd -c bcd
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "cnt[12]" and destination register "cnt[19]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC113; Fanout = 13; REG Node = 'cnt[12]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC123; Fanout = 5; REG Node = 'cnt[19]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC123; Fanout = 5; REG Node = 'cnt[19]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC113; Fanout = 13; REG Node = 'cnt[12]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "c[2]" through register "en_tmp[1]" is 27.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC118; Fanout = 37; REG Node = 'en_tmp[1]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 23.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC118; Fanout = 37; REG Node = 'en_tmp[1]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'Mux~1609'
        Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'Mux~1579'
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC86; Fanout = 1; COMB Node = 'Mux~1611'
        Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'c[2]'
        Info: Total cell delay = 19.000 ns ( 82.61 % )
        Info: Total interconnect delay = 4.000 ns ( 17.39 % )
Info: Longest tpd from source pin "a[0]" to destination pin "c[2]" is 25.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 19; PIN Node = 'a[0]'
    Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'Mux~1609'
    Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'Mux~1579'
    Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 21.000 ns; Loc. = LC86; Fanout = 1; COMB Node = 'Mux~1611'
    Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 25.000 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'c[2]'
    Info: Total cell delay = 21.000 ns ( 84.00 % )
    Info: Total interconnect delay = 4.000 ns ( 16.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Dec 13 17:32:23 2005
    Info: Elapsed time: 00:00:01