state_machine.tan.summary

CPLD VHDL CODE非常好的参考资料

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.000 ns
From           : state[2]
To             : c[5]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : lpm_counter:cnt_rtl_0|dffs[9]
To             : lpm_counter:cnt_rtl_0|dffs[19]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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