sub.hier_info

CPLD VHDL CODE非常好的参考资料

|sub
a[0] => add~0.IN4
a[1] => add~0.IN3
a[2] => add~0.IN2
a[3] => add~0.IN1
b[0] => equal~3.IN0
b[1] => equal~2.IN0
b[2] => equal~1.IN0
b[3] => equal~0.IN0
c[0] <= <VCC>
c[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <GND>
en[2] <= <GND>
en[3] <= <GND>
en[4] <= <GND>
en[5] <= <GND>
en[6] <= <GND>
en[7] <= <GND>