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📄 add.fit.eqn

📁 CPLD VHDL CODE非常好的参考资料
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L72 is Mux~2793 at SEXP107
A1L72 = EXP(a[2] & b[2] & !a[0]);


--A1L82 is Mux~2794 at SEXP105
A1L82 = EXP(!b[1] & !a[1]);


--A1L92 is Mux~2795 at SEXP104
A1L92 = EXP(!b[2] & !a[2]);


--A1L03 is Mux~2796 at SEXP101
A1L03 = EXP(b[2] & a[2]);


--A1L13 is Mux~2797 at SEXP98
A1L13 = EXP(b[1] & a[1]);


--A1L23 is Mux~2803 at LC99
A1L23_p0_out = a[2] & !b[0] & !a[0] & A1L13;
A1L23_p1_out = A1L72 & a[1] & b[1];
A1L23_p2_out = A1L82 & !a[2] & !b[2];
A1L23_p3_out = !a[1] & !b[1] & A1L92;
A1L23_p4_out = A1L03 & b[0] & a[0];
A1L23_or_out = A1L84 # A1L23_p0_out # A1L23_p1_out # A1L23_p2_out # A1L23_p3_out # A1L23_p4_out;
A1L23 = !(A1L23_or_out);


--A1L93 is Mux~2816 at SEXP82
A1L93 = EXP(!a[2] & b[1] & a[1]);


--A1L04 is Mux~2817 at LC86
A1L04_p1_out = A1L83 & A1L93 & A1L33 & A1L43 & A1L53 & A1L63 & A1L73;
A1L04_or_out = A1L04_p1_out;
A1L04 = A1L04_or_out;


--A1L14 is Mux~2824 at LC2
A1L14_p0_out = !b[0] & !a[0] & !a[1] & a[2] & b[2] & b[1];
A1L14_p1_out = !b[0] & a[0] & !a[1] & !a[2] & !b[2] & !b[1];
A1L14_p2_out = b[0] & !a[0] & !a[1] & !a[2] & !b[2] & !b[1];
A1L14_p3_out = b[0] & !a[0] & a[1] & !a[2] & b[2];
A1L14_p4_out = !b[0] & !a[0] & a[1] & a[2] & b[2] & !b[1];
A1L14_or_out = A1L94 # A1L14_p0_out # A1L14_p1_out # A1L14_p2_out # A1L14_p3_out # A1L14_p4_out;
A1L14 = A1L14_or_out;


--A1L24 is Mux~2830 at LC4
A1L24_p0_out = b[0] & a[1] & !a[2] & b[2] & b[1];
A1L24_p1_out = !b[0] & a[0] & a[1] & a[2] & !b[2];
A1L24_p2_out = !b[0] & a[0] & a[2] & !b[2] & b[1];
A1L24_p3_out = b[0] & !a[1] & a[2] & b[2] & !b[1];
A1L24_p4_out = a[0] & !a[1] & a[2] & b[2] & !b[1];
A1L24_or_out = A1L05 # A1L24_p0_out # A1L24_p1_out # A1L24_p2_out # A1L24_p3_out # A1L24_p4_out;
A1L24 = A1L24_or_out;


--A1L34 is Mux~2832 at LC93
A1L34_p1_out = b[0] & a[1] & a[2] & !b[2] & b[1];
A1L34_or_out = A1L34_p1_out # A1L14 # A1L24;
A1L34 = A1L34_or_out;


--A1L44 is Mux~2841 at LC97
A1L44_p0_out = b[0] & a[0] & a[2] & b[2] & A1L82;
A1L44_p1_out = !b[0] & !a[0] & a[2] & b[2] & a[1] & b[1];
A1L44_p2_out = !b[0] & !a[0] & !a[2] & !b[2] & a[1] & !b[1];
A1L44_p3_out = !b[0] & !a[0] & !a[2] & !b[2] & !a[1] & b[1];
A1L44_p4_out = b[0] & a[0] & !a[2] & !b[2] & !a[1] & !b[1];
A1L44_or_out = A1L44_p0_out # A1L44_p1_out # A1L44_p2_out # A1L44_p3_out # A1L44_p4_out;
A1L44 = A1L44_or_out;


--A1L54 is Mux~2848 at LC88
A1L54_p0_out = !b[0] & a[0] & a[2] & b[2] & A1L65;
A1L54_p1_out = !b[1] & b[0] & a[0] & a[1] & !a[2] & !b[2];
A1L54_p2_out = !b[1] & !b[0] & a[0] & !a[1] & !a[2] & !b[2];
A1L54_p3_out = !b[1] & b[0] & !a[0] & !a[1] & !a[2] & !b[2];
A1L54_p4_out = b[0] & !a[0] & a[2] & b[2] & A1L65;
A1L54_or_out = A1L15 # A1L54_p0_out # A1L54_p1_out # A1L54_p2_out # A1L54_p3_out # A1L54_p4_out;
A1L54 = A1L54_or_out;


--A1L64 is Mux~2854 at LC91
A1L64_p0_out = !b[2] & !a[0] & b[0];
A1L64_p1_out = !a[2] & !b[2] & !a[0] & a[1] & b[1];
A1L64_p2_out = !a[2] & !b[2] & !a[1] & b[1] & b[0];
A1L64_p3_out = !a[2] & !b[2] & a[1] & !b[1] & b[0];
A1L64_p4_out = !b[2] & a[0] & !b[0];
A1L64_or_out = A1L35 # A1L64_p0_out # A1L64_p1_out # A1L64_p2_out # A1L64_p3_out # A1L64_p4_out;
A1L64 = A1L64_or_out;


--A1L74 is Mux~2855 at LC85
A1L74_p0_out = !a[2] & !a[1] & !b[2];
A1L74_p2_out = a[0] & b[1] & !a[2] & !a[1];
A1L74_p3_out = b[1] & !a[1] & b[0] & !b[2];
A1L74_p4_out = a[0] & b[1] & !a[1] & !b[2];
A1L74_or_out = A1L55 # A1L74_p0_out # A1L74_p2_out # A1L74_p3_out # A1L74_p4_out;
A1L74 = !a[1] $ A1L74_or_out;


--A1L84 is Mux~2862 at LC98
A1L84_p1_out = !a[2] & !b[0] & !a[0] & b[2];
A1L84_p2_out = a[2] & b[0] & !a[0] & b[2];
A1L84_p3_out = a[2] & !b[0] & a[0] & b[2];
A1L84 = A1L84_p1_out # A1L84_p2_out # A1L84_p3_out;


--A1L94 is Mux~2866 at LC1
A1L94_p0_out = b[0] & a[0] & a[1] & !a[2] & !b[2] & !b[1];
A1L94_p1_out = !b[0] & !a[0] & !a[1] & a[2] & !b[2] & !b[1];
A1L94_p2_out = !b[0] & !a[0] & !a[1] & !a[2] & b[2] & !b[1];
A1L94_p3_out = !b[0] & !a[0] & a[1] & !a[2] & !b[2] & b[1];
A1L94_p4_out = b[0] & a[0] & !a[1] & !a[2] & !b[2] & b[1];
A1L94 = A1L94_p0_out # A1L94_p1_out # A1L94_p2_out # A1L94_p3_out # A1L94_p4_out;


--A1L05 is Mux~2872 at LC3
A1L05_p0_out = !b[0] & a[0] & !a[2] & b[2] & b[1];
A1L05_p1_out = b[0] & !a[0] & !a[2] & b[2] & b[1];
A1L05_p2_out = b[0] & !a[0] & a[2] & !b[2] & a[1];
A1L05_p3_out = b[0] & !a[0] & a[2] & !b[2] & b[1];
A1L05_p4_out = !b[0] & a[0] & !a[2] & b[2] & a[1];
A1L05 = A1L05_p0_out # A1L05_p1_out # A1L05_p2_out # A1L05_p3_out # A1L05_p4_out;


--A1L15 is Mux~2878 at LC87
A1L15_p1_out = !b[1] & !b[0] & !a[0] & !a[1] & a[2] & !b[2];
A1L15_p2_out = !b[1] & !b[0] & !a[0] & !a[1] & !a[2] & b[2];
A1L15_p3_out = b[1] & !b[0] & !a[0] & a[1] & !a[2] & !b[2];
A1L15_p4_out = b[1] & b[0] & a[0] & !a[1] & !a[2] & !b[2];
A1L15 = A1L15_p1_out # A1L15_p2_out # A1L15_p3_out # A1L15_p4_out;


--A1L25 is Mux~2883 at LC89
A1L25_p1_out = !a[0] & !a[1] & b[0] & !b[1];
A1L25 = A1L25_p1_out;


--A1L35 is Mux~2885 at LC90
A1L35_p0_out = !a[2] & !a[0] & !a[1] & !b[1] & b[2];
A1L35_p1_out = !a[2] & !a[0] & b[0];
A1L35_p2_out = a[0] & !b[0] & !a[1] & !b[1];
A1L35_p3_out = !a[2] & a[0] & !b[0];
A1L35_p4_out = a[2] & !a[0] & !a[1] & !b[1] & !b[2];
A1L35 = A1L25 # A1L35_p0_out # A1L35_p1_out # A1L35_p2_out # A1L35_p3_out # A1L35_p4_out;


--A1L45 is Mux~2891 at LC83
A1L45_p0_out = b[0] & b[1] & !a[2] & !b[2];
A1L45_p1_out = !b[0] & !a[0] & b[1] & a[2] & b[2];
A1L45_p2_out = b[0] & a[0] & a[2] & b[2] & a[1];
A1L45_p3_out = !b[0] & !a[0] & !b[1] & !a[2] & b[2];
A1L45_p4_out = !b[0] & !a[0] & !b[1] & a[2] & !b[2];
A1L45 = A1L45_p0_out # A1L45_p1_out # A1L45_p2_out # A1L45_p3_out # A1L45_p4_out;


--A1L55 is Mux~2897 at LC84
A1L55_p0_out = b[0] & b[1] & !a[2] & !a[1];
A1L55_p1_out = b[0] & !b[1] & a[2] & b[2];
A1L55_p2_out = b[1] & !a[2] & !b[2] & a[0];
A1L55_p3_out = !b[1] & a[2] & b[2] & a[0];
A1L55_p4_out = !b[0] & !b[1] & !a[0] & !a[1];
A1L55 = A1L45 # A1L55_p0_out # A1L55_p1_out # A1L55_p2_out # A1L55_p3_out # A1L55_p4_out;


--~VCC~0 is ~VCC~0 at LC94
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0 at LC118
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1 at LC117
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2 at LC115
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3 at LC109
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--~GND~4 is ~GND~4 at LC107
~GND~4_or_out = GND;
~GND~4 = ~GND~4_or_out;


--~GND~5 is ~GND~5 at LC105
~GND~5_or_out = GND;
~GND~5 = ~GND~5_or_out;


--~GND~6 is ~GND~6 at LC104
~GND~6_or_out = GND;
~GND~6 = ~GND~6_or_out;


--~GND~7 is ~GND~7 at LC101
~GND~7_or_out = GND;
~GND~7 = ~GND~7_or_out;


--A1L33 is Mux~2810sexp1 at SEXP81
A1L33 = EXP(b[2] & !b[1] & !a[1]);


--A1L43 is Mux~2810sexp2 at SEXP94
A1L43 = EXP(b[1] & b[0] & a[0]);


--A1L53 is Mux~2810sexp3 at SEXP93
A1L53 = EXP(b[2] & !b[0] & !a[0]);


--A1L63 is Mux~2810sexp4 at SEXP89
A1L63 = EXP(!b[1] & !b[0] & !a[0] & !a[1]);


--A1L73 is Mux~2810sexp5 at SEXP87
A1L73 = EXP(b[0] & a[0] & a[1]);


--A1L83 is Mux~2811bal at LC5
A1L83_p0_out = !b[2] & b[1] & a[1];
A1L83_p1_out = b[2] & a[2] & !b[1];
A1L83_p2_out = b[2] & a[2] & !a[1];
A1L83_p3_out = a[2] & !b[1] & !a[1];
A1L83_p4_out = a[2] & !b[0] & !a[0];
A1L83_or_out = A1L83_p0_out # A1L83_p1_out # A1L83_p2_out # A1L83_p3_out # A1L83_p4_out;
A1L83 = !(A1L83_or_out);


--a[0] is a[0] at PIN_24
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_22
--operation mode is input

a[1] = INPUT();


--a[2] is a[2] at PIN_21
--operation mode is input

a[2] = INPUT();


--b[0] is b[0] at PIN_20
--operation mode is input

b[0] = INPUT();


--b[1] is b[1] at PIN_18
--operation mode is input

b[1] = INPUT();


--b[2] is b[2] at PIN_17
--operation mode is input

b[2] = INPUT();


--c[0] is c[0] at PIN_61
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en[0] is en[0] at PIN_75
--operation mode is output

en[0] = OUTPUT(~GND~0);


--en[1] is en[1] at PIN_74
--operation mode is output

en[1] = OUTPUT(~GND~1);


--en[2] is en[2] at PIN_73
--operation mode is output

en[2] = OUTPUT(~GND~2);


--en[3] is en[3] at PIN_70
--operation mode is output

en[3] = OUTPUT(~GND~3);


--en[4] is en[4] at PIN_69
--operation mode is output

en[4] = OUTPUT(~GND~4);


--en[5] is en[5] at PIN_68
--operation mode is output

en[5] = OUTPUT(~GND~5);


--en[6] is en[6] at PIN_67
--operation mode is output

en[6] = OUTPUT(~GND~6);


--en[7] is en[7] at PIN_65
--operation mode is output

en[7] = OUTPUT(~GND~7);


--c[1] is c[1] at PIN_64
--operation mode is output

c[1] = OUTPUT(A1L23);


--c[2] is c[2] at PIN_56
--operation mode is output

c[2] = OUTPUT(A1L04);


--c[4] is c[4] at PIN_60
--operation mode is output

c[4] = OUTPUT(A1L34);


--c[5] is c[5] at PIN_63
--operation mode is output

c[5] = OUTPUT(A1L44);


--c[7] is c[7] at PIN_57
--operation mode is output

c[7] = OUTPUT(A1L54);


--c[3] is c[3] at PIN_58
--operation mode is output

c[3] = OUTPUT(A1L64);


--c[6] is c[6] at PIN_55
--operation mode is output

c[6] = OUTPUT(A1L74);






--A1L65 is Mux~2903 at SEXP86
A1L65 = EXP(!b[1] & !a[1]);


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