mlt.map.eqn

CPLD VHDL CODE非常好的参考资料

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L52 is Mux~1029
A1L52_p1_out = b[0] & a[1];
A1L52_p2_out = a[1] & b[1];
A1L52_p3_out = b[1] & a[0];
A1L52_or_out = A1L52_p1_out # A1L52_p2_out # A1L52_p3_out;
A1L52 = !(A1L52_or_out);


--A1L62 is Mux~1033
A1L62_p1_out = a[0] & b[1] & !b[0] & !a[1];
A1L62_p2_out = !a[0] & !b[1] & b[0] & a[1];
A1L62_or_out = A1L62_p1_out # A1L62_p2_out;
A1L62 = A1L62_or_out;


--A1L72 is Mux~1036
A1L72_p1_out = b[0] & a[1] & !a[0] & b[1];
A1L72_p2_out = !b[0] & a[1] & a[0] & b[1];
A1L72_or_out = A1L72_p1_out # A1L72_p2_out;
A1L72 = A1L72_or_out;


--A1L82 is Mux~1040
A1L82_p1_out = a[0] & b[0] & !a[1];
A1L82_p2_out = a[0] & !a[1] & b[1];
A1L82_p3_out = b[0] & a[1] & !b[1];
A1L82_or_out = A1L82_p1_out # A1L82_p2_out # A1L82_p3_out;
A1L82 = A1L82_or_out;


--A1L92 is Mux~1043
A1L92_p1_out = b[0] & a[0] & !a[1] & !b[1];
A1L92_p2_out = !b[0] & !a[0] & a[1] & b[1];
A1L92_or_out = A1L92_p1_out # A1L92_p2_out;
A1L92 = A1L92_or_out;


--A1L03 is Mux~1046
A1L03_p1_out = a[0] & b[0];
A1L03_p2_out = !a[0] & !b[0] & a[1] & b[1];
A1L03_or_out = A1L03_p1_out # A1L03_p2_out;
A1L03 = A1L03_or_out;


--A1L13 is Mux~1050
A1L13_p1_out = a[0] & b[0] & a[1] & b[1];
A1L13_p2_out = a[0] & b[0] & !a[1] & !b[1];
A1L13_p3_out = !a[0] & !b[0] & a[1] & b[1];
A1L13_or_out = A1L13_p1_out # A1L13_p2_out # A1L13_p3_out;
A1L13 = A1L13_or_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--~GND~4 is ~GND~4
~GND~4_or_out = GND;
~GND~4 = ~GND~4_or_out;


--~GND~5 is ~GND~5
~GND~5_or_out = GND;
~GND~5 = ~GND~5_or_out;


--~GND~6 is ~GND~6
~GND~6_or_out = GND;
~GND~6 = ~GND~6_or_out;


--~GND~7 is ~GND~7
~GND~7_or_out = GND;
~GND~7 = ~GND~7_or_out;


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(~GND~0);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(~GND~1);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(~GND~2);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(~GND~3);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(~GND~4);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(~GND~5);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(~GND~6);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(~GND~7);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(A1L52);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L62);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(A1L72);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L82);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L92);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L03);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L13);