mlt.tan.qmsg

CPLD VHDL CODE非常好的参考资料

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 15 10:37:11 2006 " "Info: Processing started: Sat Apr 15 10:37:11 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] c\[4\] 15.000 ns Longest " "Info: Longest tpd from source pin \"b\[0\]\" to destination pin \"c\[4\]\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns b\[0\] 1 PIN PIN_21 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 14; PIN Node = 'b\[0\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/" "" "" { b[0] } "NODE_NAME" } "" } } { "mlt.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/mlt.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns Mux~1050 2 COMB LC93 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'Mux~1050'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/" "" "9.000 ns" { b[0] Mux~1050 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns c\[4\] 3 PIN PIN_60 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/" "" "4.000 ns" { Mux~1050 c[4] } "NODE_NAME" } "" } } { "mlt.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/mlt.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/" "" "15.000 ns" { b[0] Mux~1050 c[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.000 ns" { b[0] b[0]~out Mux~1050 c[4] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 10:37:11 2006 " "Info: Processing ended: Sat Apr 15 10:37:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}