mlt.map.rpt

CPLD VHDL CODE非常好的参考资料

; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 16                   ;
; Total registers      ; 0                    ;
; I/O pins             ; 20                   ;
; Maximum fan-out node ; a[0]                 ;
; Maximum fan-out      ; 7                    ;
; Total fan-out        ; 44                   ;
; Average fan-out      ; 1.22                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |mlt                       ; 16         ; 20   ; |mlt                ;
+----------------------------+------------+------+---------------------+


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:mult_rtl_0            ;
+------------------------------------------------+----------+---------------------+
; Parameter Name                                 ; Value    ; Type                ;
+------------------------------------------------+----------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 2        ; Untyped             ;
; LPM_WIDTHB                                     ; 2        ; Untyped             ;
; LPM_WIDTHP                                     ; 4        ; Untyped             ;
; LPM_WIDTHR                                     ; 4        ; Untyped             ;
; LPM_WIDTHS                                     ; 1        ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped             ;
; LPM_PIPELINE                                   ; 0        ; Untyped             ;
; LATENCY                                        ; 0        ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped             ;
; USE_EAB                                        ; OFF      ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped             ;
; DEVICE_FAMILY                                  ; MAX7000S ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped             ;
+------------------------------------------------+----------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance              ;
+---------------------------------------+---------------------+
; Name                                  ; Value               ;
+---------------------------------------+---------------------+
; Number of entity instances            ; 1                   ;
; Entity Instance                       ; lpm_mult:mult_rtl_0 ;
;     -- LPM_WIDTHA                     ; 2                   ;
;     -- LPM_WIDTHB                     ; 2                   ;
;     -- LPM_WIDTHP                     ; 4                   ;
;     -- LPM_REPRESENTATION             ; UNSIGNED            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                  ;
;     -- USE_EAB                        ; OFF                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                  ;
+---------------------------------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/乘法器/mlt.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 15 10:37:02 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mlt -c mlt
Info: Found 2 design units, including 1 entities, in source file mlt.vhd
    Info: Found design unit 1: mlt-arch
    Info: Found entity 1: mlt
Info: Elaborating entity "mlt" for the top level hierarchy
Info: VHDL Case Statement information at mlt.vhd(58): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/multcore.tdf
    Info: Found entity 1: multcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "c[0]" stuck at VCC
    Warning: Pin "en[0]" stuck at GND
    Warning: Pin "en[1]" stuck at GND
    Warning: Pin "en[2]" stuck at GND
    Warning: Pin "en[3]" stuck at GND
    Warning: Pin "en[4]" stuck at GND
    Warning: Pin "en[5]" stuck at GND
    Warning: Pin "en[6]" stuck at GND
    Warning: Pin "en[7]" stuck at GND
Info: Implemented 36 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
    Info: Implemented 16 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sat Apr 15 10:37:05 2006
    Info: Elapsed time: 00:00:04