📄 clock.tan.qmsg
字号:
{ "Info" "ITDB_TSU_RESULT" "fen100:inst2\|qout rst clk 11.000 ns register " "Info: tsu for register \"fen100:inst2\|qout\" (data pin = \"rst\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns rst 1 PIN PIN_1 91 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 91; PIN Node = 'rst'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { rst } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 80 -168 0 96 "rst" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns fen100:inst2\|qout 2 REG LC114 15 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC114; Fanout = 15; REG Node = 'fen100:inst2\|qout'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "7.000 ns" { rst fen100:inst2|qout } "NODE_NAME" } "" } } { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "10.000 ns" { rst fen100:inst2|qout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { rst rst~out fen100:inst2|qout } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 40 -168 0 56 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns fen100:inst2\|qout 2 REG LC114 15 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC114; Fanout = 15; REG Node = 'fen100:inst2\|qout'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "0.000 ns" { clk fen100:inst2|qout } "NODE_NAME" } "" } } { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "3.000 ns" { clk fen100:inst2|qout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out fen100:inst2|qout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "10.000 ns" { rst fen100:inst2|qout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { rst rst~out fen100:inst2|qout } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } } { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "3.000 ns" { clk fen100:inst2|qout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out fen100:inst2|qout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg\[4\] sel:inst5\|qout\[0\] 26.000 ns register " "Info: tco from clock \"clk\" to destination pin \"seg\[4\]\" through register \"sel:inst5\|qout\[0\]\" is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 40 -168 0 56 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns fen100:inst2\|qout 2 REG LC114 15 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC114; Fanout = 15; REG Node = 'fen100:inst2\|qout'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "1.000 ns" { clk fen100:inst2|qout } "NODE_NAME" } "" } } { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns sel:inst5\|qout\[0\] 3 REG LC52 22 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC52; Fanout = 22; REG Node = 'sel:inst5\|qout\[0\]'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "8.000 ns" { fen100:inst2|qout sel:inst5|qout[0] } "NODE_NAME" } "" } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "12.000 ns" { clk fen100:inst2|qout sel:inst5|qout[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out fen100:inst2|qout sel:inst5|qout[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sel:inst5\|qout\[0\] 1 REG LC52 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC52; Fanout = 22; REG Node = 'sel:inst5\|qout\[0\]'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { sel:inst5|qout[0] } "NODE_NAME" } "" } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns decode47:inst6\|qout\[4\]~1189 2 COMB LC93 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'decode47:inst6\|qout\[4\]~1189'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "9.000 ns" { sel:inst5|qout[0] decode47:inst6|qout[4]~1189 } "NODE_NAME" } "" } } { "decode47.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/decode47.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns seg\[4\] 3 PIN PIN_60 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'seg\[4\]'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "4.000 ns" { decode47:inst6|qout[4]~1189 seg[4] } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 24 816 992 40 "seg\[7..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" { } { } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "13.000 ns" { sel:inst5|qout[0] decode47:inst6|qout[4]~1189 seg[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { sel:inst5|qout[0] decode47:inst6|qout[4]~1189 seg[4] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } } } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "12.000 ns" { clk fen100:inst2|qout sel:inst5|qout[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out fen100:inst2|qout sel:inst5|qout[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "13.000 ns" { sel:inst5|qout[0] decode47:inst6|qout[4]~1189 seg[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { sel:inst5|qout[0] decode47:inst6|qout[4]~1189 seg[4] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "fen60:inst7\|carry rst clk 15.000 ns register " "Info: th for register \"fen60:inst7\|carry\" (data pin = \"rst\", clock pin = \"clk\") is 15.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 40 -168 0 56 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns fen1:inst\|qout 2 REG LC103 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC103; Fanout = 9; REG Node = 'fen1:inst\|qout'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "1.000 ns" { clk fen1:inst|qout } "NODE_NAME" } "" } } { "fen1.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen1.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns fen60:inst3\|carry 3 REG LC34 15 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC34; Fanout = 15; REG Node = 'fen60:inst3\|carry'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "9.000 ns" { fen1:inst|qout fen60:inst3|carry } "NODE_NAME" } "" } } { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns fen60:inst7\|carry 4 REG LC50 14 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'fen60:inst7\|carry'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "8.000 ns" { fen60:inst3|carry fen60:inst7|carry } "NODE_NAME" } "" } } { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" { } { } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "21.000 ns" { clk fen1:inst|qout fen60:inst3|carry fen60:inst7|carry } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { clk clk~out fen1:inst|qout fen60:inst3|carry fen60:inst7|carry } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns rst 1 PIN PIN_1 91 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 91; PIN Node = 'rst'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { rst } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 80 -168 0 96 "rst" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns fen60:inst7\|carry 2 REG LC50 14 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'fen60:inst7\|carry'" { } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "7.000 ns" { rst fen60:inst7|carry } "NODE_NAME" } "" } } { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "10.000 ns" { rst fen60:inst7|carry } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { rst rst~out fen60:inst7|carry } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } } } 0} } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "21.000 ns" { clk fen1:inst|qout fen60:inst3|carry fen60:inst7|carry } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { clk clk~out fen1:inst|qout fen60:inst3|carry fen60:inst7|carry } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } } { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "10.000 ns" { rst fen60:inst7|carry } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { rst rst~out fen60:inst7|carry } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 23 16:37:35 2006 " "Info: Processing ended: Mon Oct 23 16:37:35 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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