clock.tan.qmsg

CPLD VHDL CODE非常好的参考资料

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 40 -168 0 56 "clk" "" } } } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fen60:inst7\|carry " "Info: Detected ripple clock \"fen60:inst7\|carry\" as buffer" {  } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fen60:inst7\|carry" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fen60:inst3\|carry " "Info: Detected ripple clock \"fen60:inst3\|carry\" as buffer" {  } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fen60:inst3\|carry" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fen1:inst\|qout " "Info: Detected ripple clock \"fen1:inst\|qout\" as buffer" {  } { { "fen1.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen1.vhd" 19 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fen1:inst\|qout" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fen100:inst2\|qout " "Info: Detected ripple clock \"fen100:inst2\|qout\" as buffer" {  } { { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 20 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fen100:inst2\|qout" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register fen24:inst4\|tem2\[1\] register sel:inst5\|qout\[1\] 31.25 MHz 32.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 31.25 MHz between source register \"fen24:inst4\|tem2\[1\]\" and destination register \"sel:inst5\|qout\[1\]\" (period= 32.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fen24:inst4\|tem2\[1\] 1 REG LC74 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC74; Fanout = 9; REG Node = 'fen24:inst4\|tem2\[1\]'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { fen24:inst4|tem2[1] } "NODE_NAME" } "" } } { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns sel:inst5\|Mux~2219 2 COMB LC40 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC40; Fanout = 1; COMB Node = 'sel:inst5\|Mux~2219'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "8.000 ns" { fen24:inst4|tem2[1] sel:inst5|Mux~2219 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns sel:inst5\|qout\[1\] 3 REG LC41 20 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC41; Fanout = 20; REG Node = 'sel:inst5\|qout\[1\]'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "1.000 ns" { sel:inst5|Mux~2219 sel:inst5|qout[1] } "NODE_NAME" } "" } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "9.000 ns" { fen24:inst4|tem2[1] sel:inst5|Mux~2219 sel:inst5|qout[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { fen24:inst4|tem2[1] sel:inst5|Mux~2219 sel:inst5|qout[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-18.000 ns - Smallest " "Info: - Smallest clock skew is -18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 40 -168 0 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns fen100:inst2\|qout 2 REG LC114 15 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC114; Fanout = 15; REG Node = 'fen100:inst2\|qout'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "1.000 ns" { clk fen100:inst2|qout } "NODE_NAME" } "" } } { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns sel:inst5\|qout\[1\] 3 REG LC41 20 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC41; Fanout = 20; REG Node = 'sel:inst5\|qout\[1\]'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "8.000 ns" { fen100:inst2|qout sel:inst5|qout[1] } "NODE_NAME" } "" } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "12.000 ns" { clk fen100:inst2|qout sel:inst5|qout[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out fen100:inst2|qout sel:inst5|qout[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 30.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 30.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 40 -168 0 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns fen1:inst\|qout 2 REG LC103 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC103; Fanout = 9; REG Node = 'fen1:inst\|qout'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "1.000 ns" { clk fen1:inst|qout } "NODE_NAME" } "" } } { "fen1.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen1.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns fen60:inst3\|carry 3 REG LC34 15 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC34; Fanout = 15; REG Node = 'fen60:inst3\|carry'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "9.000 ns" { fen1:inst|qout fen60:inst3|carry } "NODE_NAME" } "" } } { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns fen60:inst7\|carry 4 REG LC50 14 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'fen60:inst7\|carry'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "9.000 ns" { fen60:inst3|carry fen60:inst7|carry } "NODE_NAME" } "" } } { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 30.000 ns fen24:inst4\|tem2\[1\] 5 REG LC74 9 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 30.000 ns; Loc. = LC74; Fanout = 9; REG Node = 'fen24:inst4\|tem2\[1\]'" {  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "8.000 ns" { fen60:inst7|carry fen24:inst4|tem2[1] } "NODE_NAME" } "" } } { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.000 ns 80.00 % " "Info: Total cell delay = 24.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 20.00 % " "Info: Total interconnect delay = 6.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "30.000 ns" { clk fen1:inst|qout fen60:inst3|carry fen60:inst7|carry fen24:inst4|tem2[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { clk clk~out fen1:inst|qout fen60:inst3|carry fen60:inst7|carry fen24:inst4|tem2[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 6.000ns } } }  } 0}  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "12.000 ns" { clk fen100:inst2|qout sel:inst5|qout[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out fen100:inst2|qout sel:inst5|qout[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "30.000 ns" { clk fen1:inst|qout fen60:inst3|carry fen60:inst7|carry fen24:inst4|tem2[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { clk clk~out fen1:inst|qout fen60:inst3|carry fen60:inst7|carry fen24:inst4|tem2[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 30 -1 0 } }  } 0}  } { { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "9.000 ns" { fen24:inst4|tem2[1] sel:inst5|Mux~2219 sel:inst5|qout[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { fen24:inst4|tem2[1] sel:inst5|Mux~2219 sel:inst5|qout[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "12.000 ns" { clk fen100:inst2|qout sel:inst5|qout[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out fen100:inst2|qout sel:inst5|qout[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/" "" "30.000 ns" { clk fen1:inst|qout fen60:inst3|carry fen60:inst7|carry fen24:inst4|tem2[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { clk clk~out fen1:inst|qout fen60:inst3|carry fen60:inst7|carry fen24:inst4|tem2[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 6.000ns } } }  } 0}