clock.tan.summary

CPLD VHDL CODE非常好的参考资料

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.000 ns
From           : rst
To             : fen1:inst|qout
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 26.000 ns
From           : sel:inst5|qout[1]
To             : seg[3]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 15.000 ns
From           : rst
To             : fen60:inst7|carry
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 31.25 MHz ( period = 32.000 ns )
From           : fen24:inst4|tem2[0]
To             : sel:inst5|qout[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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