clock.map.rpt

CPLD VHDL CODE非常好的参考资料

; cmpconst.inc                     ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/cmpconst.inc                        ;
; lpm_compare.inc                  ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/lpm_compare.inc                     ;
; lpm_counter.inc                  ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/lpm_counter.inc                     ;
; dffeea.inc                       ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/dffeea.inc                          ;
; alt_synch_counter.inc            ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/alt_synch_counter.inc               ;
; alt_synch_counter_f.inc          ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/alt_synch_counter_f.inc             ;
; alt_counter_f10ke.inc            ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.inc               ;
; alt_counter_stratix.inc          ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc             ;
; aglobal50.inc                    ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/aglobal50.inc                       ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 69                   ;
; Total registers      ; 58                   ;
; I/O pins             ; 18                   ;
; Parallel expanders   ; 3                    ;
; Maximum fan-out node ; rst                  ;
; Maximum fan-out      ; 58                   ;
; Total fan-out        ; 557                  ;
; Average fan-out      ; 6.40                 ;
+----------------------+----------------------+


+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                   ;
+--------------------------------+------------+------+----------------------------------+
; Compilation Hierarchy Node     ; Macrocells ; Pins ; Full Hierarchy Name              ;
+--------------------------------+------------+------+----------------------------------+
; |clock                         ; 69         ; 18   ; |clock                           ;
;    |lpm_counter:div_cnt_rtl_0| ; 21         ; 0    ; |clock|lpm_counter:div_cnt_rtl_0 ;
+--------------------------------+------------+------+----------------------------------+


+----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:div_cnt_rtl_0 ;
+------------------------+----------+----------------------------------------+
; Parameter Name         ; Value    ; Type                                   ;
+------------------------+----------+----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                         ;
; LPM_WIDTH              ; 21       ; Untyped                                ;
; LPM_DIRECTION          ; UP       ; Untyped                                ;
; LPM_MODULUS            ; 0        ; Untyped                                ;
; LPM_AVALUE             ; UNUSED   ; Untyped                                ;
; LPM_SVALUE             ; UNUSED   ; Untyped                                ;
; DEVICE_FAMILY          ; MAX7000S ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                                ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                     ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                     ;
; CARRY_CNT_EN           ; SMART    ; Untyped                                ;
; LABWIDE_SCLR           ; ON       ; Untyped                                ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                                ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                                ;
+------------------------+----------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/数字时钟/clock/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Nov 23 14:26:33 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file clock.vhd
    Info: Found design unit 1: clock-arch
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Info: VHDL Case Statement information at clock.vhd(166): OTHERS choice is never selected
Info: VHDL Case Statement information at clock.vhd(226): OTHERS choice is never selected
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=21) from the following logic: "div_cnt[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[0]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 87 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 69 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Nov 23 14:26:37 2005
    Info: Elapsed time: 00:00:05