clock.fit.eqn

CPLD VHDL CODE非常好的参考资料

--G1L5 is decode47:inst6|qout[5]~1169 at LC97
G1L5_p1_out = F1_qout[1] & F1_qout[2] & F1_qout[3];
G1L5_p2_out = F1_qout[2] & F1_qout[3] & !F1_qout[0];
G1L5_p3_out = F1_qout[1] & !F1_qout[2] & !F1_qout[3] & !F1_qout[0];
G1L5_or_out = G1L5_p1_out # G1L5_p2_out # G1L5_p3_out;
G1L5 = G1L5_or_out;


--G1L2 is decode47:inst6|qout[2]~1174 at LC86
G1L2_p1_out = !F1_qout[2] & !F1_qout[3] & F1_qout[0];
G1L2_p2_out = F1_qout[2] & F1_qout[3] & F1_qout[0];
G1L2_p3_out = !F1_qout[2] & !F1_qout[3] & F1_qout[1];
G1L2_p4_out = !F1_qout[3] & F1_qout[0] & F1_qout[1];
G1L2_or_out = G1L2_p1_out # G1L2_p2_out # G1L2_p3_out # G1L2_p4_out;
G1L2 = G1L2_or_out;


--G1L6 is decode47:inst6|qout[6]~1179 at LC85
G1L6_p1_out = F1_qout[2] & !F1_qout[0] & F1_qout[1];
G1L6_p2_out = F1_qout[2] & !F1_qout[0] & F1_qout[3];
G1L6_p3_out = F1_qout[2] & F1_qout[0] & !F1_qout[1] & !F1_qout[3];
G1L6_p4_out = F1_qout[0] & F1_qout[1] & F1_qout[3];
G1L6_or_out = G1L6_p1_out # G1L6_p2_out # G1L6_p3_out # G1L6_p4_out;
G1L6 = G1L6_or_out;


--G1L7 is decode47:inst6|qout[7]~1184 at LC88
G1L7_p1_out = F1_qout[2] & F1_qout[3] & F1_qout[0];
G1L7_p2_out = F1_qout[2] & !F1_qout[3] & !F1_qout[0] & !F1_qout[1];
G1L7_p3_out = F1_qout[3] & F1_qout[0] & F1_qout[1];
G1L7_p4_out = !F1_qout[2] & !F1_qout[3] & F1_qout[0] & !F1_qout[1];
G1L7_or_out = G1L7_p1_out # G1L7_p2_out # G1L7_p3_out # G1L7_p4_out;
G1L7 = G1L7_or_out;


--G1L4 is decode47:inst6|qout[4]~1189 at LC93
G1L4_p1_out = F1_qout[2] & !F1_qout[3] & !F1_qout[1] & !F1_qout[0];
G1L4_p2_out = F1_qout[2] & F1_qout[1] & F1_qout[0];
G1L4_p3_out = !F1_qout[2] & !F1_qout[1] & F1_qout[0];
G1L4_p4_out = !F1_qout[2] & F1_qout[3] & F1_qout[1] & !F1_qout[0];
G1L4_or_out = G1L4_p1_out # G1L4_p2_out # G1L4_p3_out # G1L4_p4_out;
G1L4 = G1L4_or_out;


--C1L71 is fen100:inst2|cnt~535 at LC119
C1L71_p1_out = C1_cnt[14] & !C1_cnt[13] & C1_cnt[12] & C1_cnt[11] & C1_cnt[10] & !C1_cnt[9] & C1_cnt[8] & C1_cnt[7] & C1_cnt[5] & C1_cnt[4] & C1_cnt[3] & C1_cnt[2] & C1_cnt[1] & C1_cnt[0];
C1L71_p2_out = !C1_cnt[5] & !C1_cnt[6];
C1L71_p3_out = !C1_cnt[4] & !C1_cnt[6];
C1L71 = C1L71_p1_out # C1L71_p2_out # C1L71_p3_out;


--B1L13 is fen1:inst|cnt~378 at LC1
B1L13_p1_out = B1_cnt[25] & !B1_cnt[24] & !B1_cnt[23] & B1_cnt[22] & B1_cnt[21] & !B1_cnt[20] & !B1_cnt[19] & !B1_cnt[18] & B1_cnt[17] & !B1_cnt[16] & !B1_cnt[15] & B1_cnt[14] & !B1_cnt[13] & B1_cnt[12] & B1_cnt[11] & !B1_cnt[10] & B1_cnt[8] & C1_cnt[0] & B1_cnt[7] & B1_cnt[6] & B1_cnt[5] & B1_cnt[4] & B1_cnt[3] & B1_cnt[2] & B1_cnt[1];
B1L13 = B1L13_p1_out;


--B1L23 is fen1:inst|cnt~380 at LC2
B1L23_p0_out = !B1_cnt[9] & !B1_cnt[4];
B1L23_p1_out = !B1_cnt[8] & !B1_cnt[9];
B1L23_p2_out = !B1_cnt[9] & !B1_cnt[7];
B1L23_p3_out = !B1_cnt[9] & !B1_cnt[6];
B1L23_p4_out = !B1_cnt[9] & !B1_cnt[5];
B1L23 = B1L13 # B1L23_p0_out # B1L23_p1_out # B1L23_p2_out # B1L23_p3_out # B1L23_p4_out;


--C1L81 is fen100:inst2|LessThan~142 at LC113
C1L81_p1_out = C1_cnt[13] & C1_cnt[12] & !C1_cnt[14];
C1L81_p2_out = C1_cnt[13] & !C1_cnt[14] & C1_cnt[9] & C1_cnt[11] & C1_cnt[10] & C1_cnt[8];
C1L81_p3_out = C1_cnt[13] & !C1_cnt[14] & C1_cnt[9] & C1_cnt[11] & C1_cnt[10] & C1_cnt[6] & C1_cnt[7] & C1_cnt[5];
C1L81 = C1L81_p1_out # C1L81_p2_out # C1L81_p3_out;


--B1L43 is fen1:inst|LessThan~199 at LC4
B1L43_p1_out = B1_cnt[15] & !B1_cnt[14];
B1L43_p2_out = !B1_cnt[14] & B1_cnt[13] & B1_cnt[12];
B1L43_p3_out = !B1_cnt[14] & B1_cnt[13] & B1_cnt[9] & B1_cnt[10] & B1_cnt[11];
B1L43 = B1L43_p1_out # B1L43_p2_out # B1L43_p3_out;


--B1L53 is fen1:inst|LessThan~203 at LC102
B1L53_p1_out = !M9L3 & !M9L2 & !B1L72 & !M9L5 & !B1L82 & M9L1 & !B1L92;
B1L53 = B1L53_p1_out;


--D1L2 is fen60:inst3|carry~26 at LC33
D1L2_p1_out = !D1_tem2[1] & D1_tem2[2] & D1_tem2[0] & !D1_tem2[3] & rst & !D1_tem1[1] & !D1_tem1[2] & D1_tem1[0] & D1_tem1[3] & !D1_carry;
D1L2 = D1L2_p1_out;


--D2L2 is fen60:inst7|carry~26 at LC49
D2L2_p1_out = !D2_tem2[1] & D2_tem2[2] & D2_tem2[0] & !D2_tem2[3] & rst & !D2_tem1[1] & !D2_tem1[2] & D2_tem1[0] & D2_tem1[3] & !D2_carry;
D2L2 = D2L2_p1_out;


--F1L5 is sel:inst5|Mux~2207 at LC51
F1L5_p1_out = !D1_tem2[0] & !F1_cnt[0] & !F1_cnt[2] & !F1_cnt[1];
F1L5_p2_out = F1_cnt[1] & !D2_tem1[0] & E1_tem2[0] & !D1_tem1[0] & !D2_tem2[0];
F1L5_p3_out = !F1_cnt[0] & !F1_cnt[2] & F1_cnt[1] & !D2_tem1[0];
F1L5 = F1L5_p1_out # F1L5_p2_out # F1L5_p3_out;


--F1L6 is sel:inst5|Mux~2211 at LC35
F1L6_p1_out = !E1_tem2[2] & !D1_tem1[2] & !D2_tem1[2] & !D2_tem2[2] & F1_cnt[1];
F1L6_p2_out = !E1_tem2[2] & F1_cnt[1] & F1_cnt[2] & !F1_cnt[0];
F1L6_p3_out = !D1_tem1[2] & F1_cnt[1] & F1_cnt[2] & F1_cnt[0];
F1L6 = F1L6_p1_out # F1L6_p2_out # F1L6_p3_out;


--F1L7 is sel:inst5|Mux~2215 at LC37
F1L7_p1_out = !E1_tem2[3] & !D1_tem1[3] & !D2_tem1[3] & F1_cnt[1] & !D2_tem2[3];
F1L7_p2_out = !E1_tem2[3] & F1_cnt[1] & !F1_cnt[0] & F1_cnt[2];
F1L7_p3_out = !F1_cnt[1] & F1_cnt[0] & F1_cnt[2] & !E1_tem1[3];
F1L7 = F1L7_p1_out # F1L7_p2_out # F1L7_p3_out;


--F1L8 is sel:inst5|Mux~2219 at LC40
F1L8_p1_out = !E1_tem2[1] & !D1_tem1[1] & !D2_tem2[1] & !D2_tem1[1] & F1_cnt[1];
F1L8_p2_out = !E1_tem2[1] & F1_cnt[1] & !F1_cnt[0] & F1_cnt[2];
F1L8_p3_out = !D1_tem1[1] & F1_cnt[1] & F1_cnt[0] & F1_cnt[2];
F1L8 = F1L8_p1_out # F1L8_p2_out # F1L8_p3_out;


--~VCC~0 is ~VCC~0 at LC94
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--rst is rst at PIN_1
--operation mode is input

rst = INPUT();


--seg[0] is seg[0] at PIN_61
--operation mode is output

seg[0] = OUTPUT(~VCC~0);


--sel[7] is sel[7] at PIN_65
--operation mode is output

sel[7] = OUTPUT(F1_sel[7]);


--sel[6] is sel[6] at PIN_67
--operation mode is output

sel[6] = OUTPUT(F1_sel[6]);


--sel[5] is sel[5] at PIN_68
--operation mode is output

sel[5] = OUTPUT(F1_sel[5]);


--sel[4] is sel[4] at PIN_69
--operation mode is output

sel[4] = OUTPUT(F1_sel[4]);


--sel[3] is sel[3] at PIN_70
--operation mode is output

sel[3] = OUTPUT(F1_sel[3]);


--sel[2] is sel[2] at PIN_73
--operation mode is output

sel[2] = OUTPUT(F1_sel[2]);


--sel[1] is sel[1] at PIN_74
--operation mode is output

sel[1] = OUTPUT(F1_sel[1]);


--sel[0] is sel[0] at PIN_75
--operation mode is output

sel[0] = OUTPUT(F1_sel[0]);


--seg[3] is seg[3] at PIN_58
--operation mode is output

seg[3] = OUTPUT(G1L3);


--seg[1] is seg[1] at PIN_64
--operation mode is output

seg[1] = OUTPUT(G1L1);


--seg[6] is seg[6] at PIN_55
--operation mode is output

seg[6] = OUTPUT(G1L6);


--seg[5] is seg[5] at PIN_63
--operation mode is output

seg[5] = OUTPUT(G1L5);


--seg[2] is seg[2] at PIN_56
--operation mode is output

seg[2] = OUTPUT(G1L2);


--seg[7] is seg[7] at PIN_57
--operation mode is output

seg[7] = OUTPUT(G1L7);


--seg[4] is seg[4] at PIN_60
--operation mode is output

seg[4] = OUTPUT(G1L4);