clock.map.rpt

CPLD VHDL CODE非常好的参考资料

;    |decode47:inst6|                   ; 7          ; 0    ; |clock|decode47:inst6                                                           ;
;    |fen100:inst2|                     ; 18         ; 0    ; |clock|fen100:inst2                                                             ;
;    |fen1:inst|                        ; 41         ; 0    ; |clock|fen1:inst                                                                ;
;       |lpm_add_sub:add_rtl_1|         ; 6          ; 0    ; |clock|fen1:inst|lpm_add_sub:add_rtl_1                                          ;
;          |addcore:adder[2]|           ; 5          ; 0    ; |clock|fen1:inst|lpm_add_sub:add_rtl_1|addcore:adder[2]                         ;
;             |a_csnbuffer:result_node| ; 5          ; 0    ; |clock|fen1:inst|lpm_add_sub:add_rtl_1|addcore:adder[2]|a_csnbuffer:result_node ;
;          |addcore:adder[3]|           ; 1          ; 0    ; |clock|fen1:inst|lpm_add_sub:add_rtl_1|addcore:adder[3]                         ;
;             |a_csnbuffer:result_node| ; 1          ; 0    ; |clock|fen1:inst|lpm_add_sub:add_rtl_1|addcore:adder[3]|a_csnbuffer:result_node ;
;    |fen24:inst4|                      ; 8          ; 0    ; |clock|fen24:inst4                                                              ;
;    |fen60:inst3|                      ; 10         ; 0    ; |clock|fen60:inst3                                                              ;
;    |fen60:inst7|                      ; 10         ; 0    ; |clock|fen60:inst7                                                              ;
;    |sel:inst5|                        ; 19         ; 0    ; |clock|sel:inst5                                                                ;
+---------------------------------------+------------+------+---------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: fen100:inst2|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name         ; Value       ; Type                                         ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH              ; 15          ; Untyped                                      ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                      ;
; LPM_DIRECTION          ; ADD         ; Untyped                                      ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                      ;
; LPM_PIPELINE           ; 0           ; Untyped                                      ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                      ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                           ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                                      ;
; USE_WYS                ; OFF         ; Untyped                                      ;
; STYLE                  ; FAST        ; Untyped                                      ;
; CBXI_PARAMETER         ; add_sub_9ph ; Untyped                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                               ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: fen1:inst|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+-------------------------------------------+
; Parameter Name         ; Value       ; Type                                      ;
+------------------------+-------------+-------------------------------------------+
; LPM_WIDTH              ; 26          ; Untyped                                   ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                   ;
; LPM_DIRECTION          ; ADD         ; Untyped                                   ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                   ;
; LPM_PIPELINE           ; 0           ; Untyped                                   ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                   ;
; REGISTERED_AT_END      ; 0           ; Untyped                                   ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                   ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                   ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                   ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                        ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                                   ;
; USE_WYS                ; OFF         ; Untyped                                   ;
; STYLE                  ; FAST        ; Untyped                                   ;
; CBXI_PARAMETER         ; add_sub_bph ; Untyped                                   ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                            ;
+------------------------+-------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Oct 23 16:37:19 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.bdf
    Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file decode47.vhd
    Info: Found design unit 1: decode47-behave
    Info: Found entity 1: decode47
Info: Found 2 design units, including 1 entities, in source file sel.vhd
    Info: Found design unit 1: sel-behave
    Info: Found entity 1: sel
Info: Found 2 design units, including 1 entities, in source file fen60.vhd
    Info: Found design unit 1: fen60-behave
    Info: Found entity 1: fen60
Info: Found 2 design units, including 1 entities, in source file fen24.vhd
    Info: Found design unit 1: fen24-behave
    Info: Found entity 1: fen24
Info: Found 2 design units, including 1 entities, in source file fen1.vhd
    Info: Found design unit 1: fen1-behave
    Info: Found entity 1: fen1
Info: Found 2 design units, including 1 entities, in source file fen100.vhd
    Info: Found design unit 1: fen100-behave
    Info: Found entity 1: fen100
Info: Elaborating entity "clock" for the top level hierarchy
Info: Elaborating entity "decode47" for hierarchy "decode47:inst6"
Info: Elaborating entity "sel" for hierarchy "sel:inst5"
Info: Elaborating entity "fen100" for hierarchy "fen100:inst2"
Info: Elaborating entity "fen60" for hierarchy "fen60:inst3"
Warning: VHDL Process Statement warning at fen60.vhd(49): signal "tem1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fen60.vhd(50): signal "tem2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "fen1" for hierarchy "fen1:inst"
Info: Elaborating entity "fen24" for hierarchy "fen24:inst4"
Warning: VHDL Process Statement warning at fen24.vhd(55): signal "tem1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fen24.vhd(56): signal "tem2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 41 buffer(s)
    Info: Ignored 41 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register "fen1:inst|cnt[0]" merged to single register "fen100:inst2|cnt[0]"
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seg[0]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 132 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 114 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Mon Oct 23 16:37:28 2006
    Info: Elapsed time: 00:00:09