traffic.tan.qmsg

CPLD VHDL CODE非常好的参考资料

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:div_cnt_rtl_0\|dffs\[15\] " "Info: Detected ripple clock \"lpm_counter:div_cnt_rtl_0\|dffs\[15\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:div_cnt_rtl_0\|dffs\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:div_cnt_rtl_0\|dffs\[24\] " "Info: Detected ripple clock \"lpm_counter:div_cnt_rtl_0\|dffs\[24\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:div_cnt_rtl_0\|dffs\[24\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state\[1\] register second\[1\] 71.43 MHz 14.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 71.43 MHz between source register \"state\[1\]\" and destination register \"second\[1\]\" (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[1\] 1 REG LC83 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC83; Fanout = 36; REG Node = 'state\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "" { state[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns second\[1\]~207 2 COMB LC104 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC104; Fanout = 1; COMB Node = 'second\[1\]~207'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "8.000 ns" { state[1] second[1]~207 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns second\[1\] 3 REG LC105 47 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC105; Fanout = 47; REG Node = 'second\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "1.000 ns" { second[1]~207 second[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "9.000 ns" { state[1] second[1]~207 second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { state[1] second[1]~207 second[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[24\] 2 REG LC113 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC113; Fanout = 11; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[24\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "1.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns second\[1\] 3 REG LC105 47 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC105; Fanout = 47; REG Node = 'second\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "8.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[24\] 2 REG LC113 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC113; Fanout = 11; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[24\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "1.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns state\[1\] 3 REG LC83 36 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC83; Fanout = 36; REG Node = 'state\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "8.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "9.000 ns" { state[1] second[1]~207 second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { state[1] second[1]~207 second[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] second[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] state[1] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] first\[0\] 34.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"first\[0\]\" is 34.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[24\] 2 REG LC113 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC113; Fanout = 11; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[24\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "1.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns first\[0\] 3 REG LC96 51 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC96; Fanout = 51; REG Node = 'first\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "8.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[24] first[0] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] first[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] first[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.000 ns + Longest register pin " "Info: + Longest register to pin delay is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns first\[0\] 1 REG LC96 51 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC96; Fanout = 51; REG Node = 'first\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "" { first[0] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns Mux~3544 2 COMB SEXP98 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP98; Fanout = 1; COMB Node = 'Mux~3544'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "10.000 ns" { first[0] Mux~3544 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 17.000 ns Mux~3549 3 COMB LC97 1 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 17.000 ns; Loc. = LC97; Fanout = 1; COMB Node = 'Mux~3549'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "7.000 ns" { Mux~3544 Mux~3549 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 21.000 ns dataout\[5\] 4 PIN PIN_63 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 21.000 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'dataout\[5\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "4.000 ns" { Mux~3549 dataout[5] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 90.48 % " "Info: Total cell delay = 19.000 ns ( 90.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 9.52 % " "Info: Total interconnect delay = 2.000 ns ( 9.52 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "21.000 ns" { first[0] Mux~3544 Mux~3549 dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { first[0] Mux~3544 Mux~3549 dataout[5] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "12.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[24] first[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[24] first[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/" "" "21.000 ns" { first[0] Mux~3544 Mux~3549 dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { first[0] Mux~3544 Mux~3549 dataout[5] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 15:17:53 2005 " "Info: Processing ended: Wed Nov 23 15:17:53 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}