traffic.map.qmsg

CPLD VHDL CODE非常好的参考资料

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 23 15:17:39 2005 " "Info: Processing started: Wed Nov 23 15:17:39 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file traffic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 traffic-arch " "Info: Found design unit 1: traffic-arch" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic " "Info: Elaborating entity \"traffic\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "traffic.vhd(182) " "Info: VHDL Case Statement information at traffic.vhd(182): OTHERS choice is never selected" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 182 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "div_cnt\[0\]~0 25 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=25) from the following logic: \"div_cnt\[0\]~0\"" {  } { { "traffic.vhd" "div_cnt\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 22 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 32 -1 0 } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "en_xhdl\[1\] en_xhdl\[0\] " "Info: Duplicate register \"en_xhdl\[1\]\" merged to single register \"en_xhdl\[0\]\", power-up level changed" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 32 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/综合实验/交通灯/traffic/traffic.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "100 " "Info: Implemented 100 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "68 " "Info: Implemented 68 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "8 " "Info: Implemented 8 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 15:17:45 2005 " "Info: Processing ended: Wed Nov 23 15:17:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}