bvdisrs.c

PXA27X_CAYMAN BSP from CAYMAN board

            GEDR_GPIO14_EDGE_CLR(v_pGPIOReg->GEDR0);

            if(v_PCMCIA->status & PCMCIA0_CD)
            {
                GFER_GPIO17_DISABLE(v_pGPIOReg->GFER0);    //doesn't insert card
            }
            else
            {
                GPIO17_FALLING_EDGE_ON(v_pGPIOReg->GFER0);    //insert card
            }


            v_pDrvGlob->pcm.slot0CDvalidint = 1;
            interruptType = SYSINTR_PCMCIA_STATE;
        }

        if(v_PCMCIA->intr & PCMCIA1_INT_ENABLE)
        {

            while(!(v_PCMCIA->status & PCMCIA_CONTROL_IDLE));
	        v_PCMCIA->intrmask &= PCMCIA1_MASK;
	     
            GPIO14_FALLING_EDGE_OFF(v_pGPIOReg->GEDR0);
            GEDR_GPIO14_EDGE_CLR(v_pGPIOReg->GEDR0);

            if(v_PCMCIA->status & PCMCIA1_CD)
            {
                GFER_GPIO108_DISABLE(v_pGPIOReg->GFER3);    //doesn't insert card
            }
            else
            {
                GPIO108_FALLING_EDGE_ON(v_pGPIOReg->GFER3);    //insert card
            }
            v_pDrvGlob->pcm.slot1CDvalidint = 1;
            interruptType = SYSINTR_PCMCIA_STATE;
        }
        GEDR_GPIO14_EDGE_CLR(v_pGPIOReg->GEDR0);
        
    }
    else if(v_pGPIOReg->GEDR0 & 0x20000)       
    {
        GEDR_GPIO17_EDGE_CLR(v_pGPIOReg->GEDR0);
        v_pDrvGlob->pcm.slot0Enable = 1;
        interruptType = SYSINTR_PCMCIA_LEVEL;
    }
    else if(v_pGPIOReg->GEDR3 & 0x1000)
    {
        GEDR_GPIO108_EDGE_CLR(v_pGPIOReg->GEDR3);
        v_pDrvGlob->pcm.slot1Enable = 1;
        interruptType = SYSINTR_PCMCIA_LEVEL;
    }
    else
    {
    	interruptType = SYSINTR_NOP;
    }
    
    INTC_GPIOXX_2_INT_EN(v_pICReg->icmr);
    return interruptType;
}


//
// MMCISR
//
// MMC ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int MMCISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	INTC_MMC_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_SDMMC;
}

//
// KEYPADISR
//
// KeyPad ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int KEYPADISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;


	INTC_KEYPAD_INT_DIS(v_pICReg->icmr);
#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_KEYPAD;
}

//
// UDCISR
//
// UDC Device Controller ISR (USB Function)
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int UDCISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
    // UDC - USB Device Controller
	// mask the USB interrupt
    //
	INTC_USBC_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_USB_CLIENT;
}

//
// FFUARTISR
//
// FullFeatured UART
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int FFUARTISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	//
    // FFUART interrupt 
    // mask the interrupt
    //
	INTC_FFUART_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_SERIAL;
}

//
// BTUARTISR
//
// BlueTooth UART
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int BTUARTISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	//
    // BTUART interrupt 
    // mask the interrupt
    //
	INTC_BTUART_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_SERIAL2;
}

//
// STDUARTISR
//
// Standard UART - IrDA 
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int STDUARTISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
    // STDUART interrupt - IrDA port
    // mask the interrupt
    //
	INTC_STUART_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_IR;
}

//
// DMACISR
//
// DMA Controller ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int DMACISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
	   volatile DMAC_REGS	*v_pDMAReg;

    v_pDMAReg = (volatile DMAC_REGS *)DMAC_BASE_U_VIRTUAL; 
    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

		
	// 
	// DMAC interrupt (Interrupt Mask 25)
	// 
    //
    // Mask interrupt
    //
	   INTC_DMAC_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	   {
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

   	// Determine the nature of the interrupt
   
   	//
   	//AC97 Audio Interrupt
   	//
   	if (v_pDMAReg->dint & DMA_AUDIO_INTR)	// The DMAC had some kind of AUDIO interrupt
   	{
   		  return SYSINTR_AUDIO;
   	}
   	else if (v_pDMAReg->dint & DMA_CAMERA_INTR)
   	{
   		  return SYSINTR_CAMERA_DMAC;
   	}
   	else
   	{
   		//
   		// if we get here then an unexpected DMA interrupt occured
   		// 
   		DEBUGCHK(0); 
   		return SYSINTR_NOP;
   	}
}

//
// Chainable ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
//  Call the kernel and chain to the installable ISR
// 
int ChainableISR(unsigned int ra)
{
	   DWORD			sysIntrValue,
				devID;
    unsigned long	devBit;
    volatile XLLP_INTC_T  *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

   	//
   	// Get interrupting device ID and bit mask
   	// 
   	devID = v_pICReg->ichp & 0x0000001F;
   
       //
       // Chain to the ISR, if one is installed
       //
   	sysIntrValue = NKCallIntChain ((BYTE)devID);	// Device Interrupt ID
   	
   	if (sysIntrValue == SYSINTR_CHAIN)
   	{
           //
           // No installable isr to handle this interrupt
   		// disable the interrupt
           //
   		   devBit = (0x1 << devID);
   		   v_pICReg->icmr &= ~devBit;
   		   sysIntrValue = SYSINTR_NOP;
    }
   
   	return sysIntrValue;

}


//
// PMU ISR
//
// Needs to be modified for FIQ
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int PMUISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
    // Service the PMU interrupt
    //

    //
    // PVTuneInterrupt is initialized when the callback routine 
    // is registered, otherwise it's NULL.
    //
    if(PVTuneInterrupt)
    {
        SampleInput     StateData;
		BOOL			bBufferFull;


		//
		// Mask interrupt
		//
        INTC_PMU_INT_DIS (v_pICReg->icmr);


        // Grab sample data for VTune
        // ra (interrupted address),
        // SPSR,
        // TID,
        // PID
	    // 
        StateData.r14 = ra;
        StateData.spsr = XSC1GetSPSR();
        StateData.tid = GetCurrentThreadId();
        StateData.pid = GetCurrentProcessId();

        //
        // Call the PMU interrupt callback routine to buffer the
        // processor state.  Callback returns TRUE if post-processing
        // is necessary (buffer is full). If post-processing is needed,
        // signal VTune PMU IST (SYSINTR_PMU), otherwise return SYSINTR_NOP.
        //
        // Note:  PVTuneInterrupt initialized in oemioctl in 
        //        PMU_ENABLE_IRQ processing.  Resolved to address kernel
        //        can access in PMU API.
        //
		//
		bBufferFull = PVTuneInterrupt(&StateData);

		//
		// Unmask interrupt
		//
        INTC_PMU_INT_EN (v_pICReg->icmr);


		if (bBufferFull)
		{
            return SYSINTR_PMU;
		}
    }
    else
    {
        //
        // No PMU interrupt registered -> disable the interrupt
        //
        INTC_PMU_INT_DIS (v_pICReg->icmr);
        bPMURunning = FALSE;
    }
    //
    // No post-processing needed.
    //
    return SYSINTR_NOP;
}


//
// USBOHCISTATISR
//
// USB Host OHCI Controller Status ISR (USB Host)
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int USBOHCIISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
  
   	v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
	// mask the USB Host interrupt
    //
	   INTC_USBOHCI_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	   {
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	   return SYSINTR_OHCI_MDD;
}

//
// USBOHCIEVENTISR
//
// USB Host OHCI Controller Event: abort, power, misc. ISR (USB Host)
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int USBNONOHCIISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
	// mask the USB Host interrupt
    //
	   INTC_USBNONOHCI_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	   {
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

   	return SYSINTR_OHCI_PDD;
}

//
// Bulverde Capture interface ISR
//
// Delivers an End Of Frame interrupt
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//

int BvdCIISR(unsigned int ra)
{
	   volatile XLLP_INTC_T *v_pICReg;

	   v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	   INTC_CAPTURE_INT_DIS(v_pICReg->icmr2);
	   

	   return SYSINTR_CAMERA_INTERFACE;
}

static XLLP_OST_T *pOSTRegs = NULL;
void OEMSleep(DWORD dwMS)
{
    /*
     * If we're not in a power handler, use Sleep to block our
     * thread and let others run.  Note that Sleep() currently
     * is more accurate for low values than 2.12- the minimum sleep
     * interval is at least one system tick (25 ms) for 2.12, whereas
	 * now it is 1ms.  Of course, if a higher priority thread is ready
	 * to run when this is woken, we will see a longer wait.
     *
     */
    pOSTRegs = (XLLP_OST_T *)OST_BASE_U_VIRTUAL;
	XllpOstDelayMilliSeconds(pOSTRegs, dwMS);
} // DriverSleep()

//
// LCD Controller ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//

int LCDISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
    volatile LCDRegs *v_pLCDRegs;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;
    v_pLCDRegs = (volatile LCDRegs *)LCD_BASE_U_VIRTUAL;

    INTC_LCD_INT_DIS(v_pICReg->icmr);
    
    if(v_pLCDRegs->LCSR0 & LCD_OU)
    {
        //DWORD oldLCCR3, oldPCD;
        v_pLCDRegs->LCCR0 |= LCD_OUM;
        v_pLCDRegs->LCSR0 |= LCD_OU;
        //oldLCCR3 = v_pLCDRegs->LCCR3;
        //oldPCD   = oldLCCR3 & 0xFF;

//        v_pLCDRegs->LCCR0 &= ~LCD_ENB;

        //v_pLCDRegs->LCCR3 = oldLCCR3 & 0xFFFFFF00 + (oldPCD << 2) & 0xFF;
        
        //EdbgOutputDebugString("2");
        //OEMSleep(1);

        //v_pLCDRegs->LCCR3 = oldLCCR3;        
        v_pLCDRegs->LCCR0 &= ~LCD_OUM;
//        v_pLCDRegs->LCCR0 |= LCD_ENB;
    }
        
    INTC_LCD_INT_EN(v_pICReg->icmr);	   
    return SYSINTR_NOP;
}