fwbvd1.s

PXA27X_CAYMAN BSP from CAYMAN board

        bic     r4,  r4,  #MDREFR_SLFRSH
        
        ; write back mdrefr
        ;
        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]
        
        ; 3rd Bullet: assert E1PIN
        ;
        orr     r4,  r4,  #MDREFR_E1PIN
        
        ; write back mdrefr
        ;
        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]
        nop
        nop



; ****************************************************************************
;   Step 4: Configure, but don't enable each SDRAM partition pair
;

        ; fetch platform value of mdcnfg
        ;
        ldr     r2,  =MDCNFG_VAL        
    
        ; disable all sdram banks
        ;
        bic     r2,  r2,  #(MDCNFG_DE0 :OR: MDCNFG_DE1)
        bic     r2,  r2,  #(MDCNFG_DE2 :OR: MDCNFG_DE3)

        ; Configure port width
        ;
        bic   r2,  r2,  #MDCNFG_DWID0      ; 0: 32-bit

        ; write initial value of mdcnfg, w/o enabling sdram banks
        ;
        str     r2,  [r1, #MDCNFG_OFFSET]


; ****************************************************************************
;   Step 5
;

        ; pause for 200 uSecs
        ;
        ldr r3, =OST_BASE_PHYSICAL                      ; reset the OS Timer Count to zero
        ldr r2, [r3, #OSCR0_OFFSET] 
        ldr r4, =0x300          ; really 0x2E1 is about 200usec, so 0x300 should be plenty
10
        ldr r0, [r3, #OSCR0_OFFSET] 
        sub r0, r0, r2
        cmp r4, r0
        bgt %B10
        

; ****************************************************************************
;   Step 6
;

        mov    r0, #0x78                    ; turn everything off 
        mcr    p15, 0, r0, c1, c0, 0        ; Redundant: (caches off, MMU off, etc.)


        
; ****************************************************************************
;   Step 7
;
        ;  Access memory *not yet enabled* for CBR refresh cycles (8)
        ;  - CBR is generated for all banks
        
        tst     r10, #(xlli_RCSR_SMR:OR:xlli_RCSR_GPR) ;
        bne     %F12                ; skip if sleep (or GPIO) reset.
        ldr     r2, =SDRAM_BASE_PHYSICAL
        str     r2, [r2]
        str     r2, [r2]
        str     r2, [r2]
        str     r2, [r2]
        str     r2, [r2]
        str     r2, [r2]
        str     r2, [r2]
        str     r2, [r2]
    ; Fix for erratum #116.  Need to make up for ineffective first mem access.
    ;   *Bman: leaving in for Bulverde, as I expect this errata to also exist there.
    ;
        str     r2, [r2]

12  ; skipped due to sleep (or GPIO) reset

; ****************************************************************************
;   Step 8: NOP (enable dcache if you wanna... we dont)
;


; ****************************************************************************
;   Step 9:  Enable the SDRAM partitions
;

        ; get memory controller base address
        ;
        ldr     r1,  =MEMC_BASE_PHYSICAL

        ; fetch current mdcnfg value
        ;
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        ; enable sdram bank 0 if installed (must do for any populated bank)
        ;
        orr     r3,  r3,  #MDCNFG_DE0

        IF  :DEF: MEM128M
        orr     r3,  r3,  #MDCNFG_DE1
        ENDIF
        ; write back mdcnfg, enabling the sdram bank(s)
        ;
        str     r3,  [r1, #MDCNFG_OFFSET]

        

; ****************************************************************************
;   Step 10: Write Mode Register Set to enabled SDRAM partitions
;
        
        ; write mdmrs
        ;
        ldr     r2,  =MDMRS_VAL
        str     r2,  [r1, #MDMRS_OFFSET]

        ; bman: when do we write mdmrs_sleep?*
        ; i'll do it now... yeah, and we die if i do!  cannot write to sdram it i do this here
        ;
        ldr     r2, =MDMRSLP_VAL
        str     r2,  [r1, #MDMRSLP_OFFSET]
        
        
; ****************************************************************************
;   Step 11: Final Step: Enable APD if desired.  BMAN:  ok for sync FLASH? (not configged yet, but will be shortly after)*
;
        
        ;ldr     r3,  [r1, #MDREFR_OFFSET]
        
        ; enable auto-power down 
        ;
        ;orr     r3,  r3,  #MDREFR_APD
        
        ; write back mdrefr
        ;
        ;str     r3,  [r1, #MDREFR_OFFSET]  ; bman: try without just in case is causing me pain... 

    
   ALIGN
NOBUFFERMUCKYMUCK


         mov  pc, lr
    

;;
;; End of INITMEMC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


    LTORG       ; Insert a literal pool here
    
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITINTC        
        ; ********************************************************************
        ; Disable (mask) all interrupts at the interrupt controller
        ;

        ; clear the interrupt level register (use IRQ, not FIQ)
        ;
        mov     r1, #0
        ldr     r2,  =INTC_BASE_PHYSICAL
        str     r1,  [r2, #ICLR_OFFSET]
        
        ; mask all interrupts at the controller
        ;        
        str     r1,  [r2, #ICMR_OFFSET]

        ; set DIM: may move out to OEMInit for visibility
        ;
        mov     r1, #1
        str     r1, [r2, #ICCR_OFFSET]

         mov  pc, lr
    

   
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITCLKS        
        
        ldr     r1,  =CLK_BASE_PHYSICAL
        
        ; Turn only clocks that are necessary (MEMC, OST, FFUART)
        ;
        ldr     r2,  =CKEN_DEFAULT
        str     r2,  [r1, #CKEN_OFFSET]

        ;ldr     r2,  =0x02000290                ; 104MHz * 2 * 2.5 = 520MHz
        ldr     r2,  =0x00000290                ; 104MHz * 2 * 2.5 = 520MHz
        ;ldr     r2,  =0x00000214                ; 130MHz * 2 * 2   = 520MHz
        ;ldr     r2,  =0x02000310                ; 104MHz * 2 * 3   = 624MHz
        ;ldr     r2,  =0x00000294                ; 130MHz * 2 * 2.5  = 650MHz
        ldr     r1,  =CLK_BASE_PHYSICAL
        str     r2,  [r1, #CCCR_OFFSET]

        ; enable 32KHz OSC output on GPIO[10] (CLK_TOUT) and
        ;  enable 13MHz output on GPIO[9] (CLK_PIO)...
        ;
        ldr     r2, [r1, #OSCC_OFFSET]
        and     r2, r2, #0xF3
        ;orr     r2, r2, #(OSCC_TOUT_EN)        ;#(OSCC_TOUT_EN :OR: OSCC_PIO_EN)
        str     r2,  [r1, #OSCC_OFFSET]
	
        ;
        ; initiate the frequency change sequence
        ;
        mov   r2, #0xB
        mcr p14, 0, r2, c6, c0, 0       ; write CCLKCFG
        
        ;
        ; ReWrite MDREFR[DRI] regardless
        ;
        ldr     r1,  =MEMC_BASE_PHYSICAL
        
        ldr     r2,  [r1, #MDREFR_OFFSET]
        ldr     r3,  =0x3fddefff                        ; mask off reserved bits.  *bman: use equ here...
        and     r2,  r2, r3
        str     r2,  [r1, #MDREFR_OFFSET]
        
        mov  pc, lr
    

    LTORG       ; Insert a literal pool here


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Matrix used for optmial LC, based on L param of CCSR
;
   ALIGN 16             ; Start array on 16B boundary for index scheme: Index = &L0 + 'L'
L_0      DCB     3       ; placeholder
L_1      DCB     3       ; placeholder
L_2      DCB     3       ; * close
L_3      DCB     5
L_4      DCB     3
L_5      DCB     5
L_6      DCB     5
L_7      DCB     6
L_8      DCB     3       ; * close
L_9      DCB     4
L_A      DCB     4
L_B      DCB     5
L_C      DCB     5
L_D      DCB     5       ; * close
L_E      DCB     6
L_F      DCB     6
L_10     DCB     3       ; * close

L_11     DCB     0       ; * DE-FEATURED
L_12     DCB     0       ; * DE-FEATURED
L_13     DCB     0       ; * DE-FEATURED
L_14     DCB     0       ; * DE-FEATURED
L_15     DCB     0       ; * DE-FEATURED
L_16     DCB     0       ; * DE-FEATURED
L_17     DCB     0       ; * DE-FEATURED
L_18     DCB     0       ; * DE-FEATURED
L_19     DCB     0       ; * DE-FEATURED
L_1A     DCB     0       ; * DE-FEATURED
L_1B     DCB     0       ; * DE-FEATURED
L_1C     DCB     0       ; * DE-FEATURED

L_1D     DCB     6
L_1E     DCB     6
L_1F     DCB     3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITOST        
        ; ********************************************************************
        ; Initialize the OST count register to zero.
        ;

        ldr   r1,  =OST_BASE_PHYSICAL
        mov   r2,  #0
        str   r2,  [r1, #OSCR0_OFFSET]

         mov  pc, lr



;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITRTC        
        ; ********************************************************************            
        ; Initialize the RTC count register to zero.  Currently not adjusting
        ;   the trim reg (RTTR).
        ;

        ldr     r1,  =RTC_BASE_PHYSICAL
        mov     r2,  #0
        str     r2,  [r1, #RCNR_OFFSET]


         mov  pc, lr



;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITPWRMAN        
        ; ********************************************************************            
        ; Initialize the power mgr registers.
        ;

        ; get base address of power mgr / reset control regs
        ;
        ldr     r2,  =PWR_BASE_PHYSICAL

        ; init the pmcr: done in preinit

        ; *NOTE: PSSR is initialized at the end of INITGPIO
        
        
        ; init the PCFR
        ; *NOTE:  only configuring OPDE & SYSEN_EN here; power management and DVM code will care about many bits in this register.
        ;
        mov     r1, #(PCFR_OPDE)    
        str     r1, [r2, #PCFR_OFFSET]

        ; taking POR for PWER: GPIO[1:0] enabled for wakeup sources
        
        ; taking POR for PRER, PFER, PEDR.

        ; taking POR for PGSR[3:0]
        
        ; taking POR for RCSR; resume code will consume
        
        ; taking POR for PSLR, PSTR, PSNR for now; will tweak at a later time for power management concerns
        
        ; taking POR for PVCR, PCMD[31:0]; DVM concern
        
        ; taking POR for PKWR, PKSR

    

         mov  pc, lr

 LTORG       ; Insert a literal pool here


;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
SCRUB_SDRAM