fwbvd1.s

PXA27X_CAYMAN BSP from CAYMAN board

 	 ldr		r2, =0x3
        str     r2, [r1, #GPSR1_OFFSET]
        ldr     r2, =0x00018000
        str     r2, [r1, #GPSR2_OFFSET]


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        ldr 	r2,	 =0xD84189E4
        str     r2,  [r1, #GPDR0_OFFSET]

        ldr     r2,  =0x00BFA983
        str     r2,  [r1, #GPDR1_OFFSET]


        ldr     r2,  =0xCE01FC00
        str     r2,  [r1, #GPDR2_OFFSET]

        ldr	r2,	 =0x008a0100
        str     r2,  [r1, #GPDR3_OFFSET]


        ; Finally, set GAFR0,1,2,3 for alternate functions
        ;
	
        ;set gpio15 to nCS<1> wangshu 2004-11-30
        ldr     r2, =0x83C00000         
        str     r2, [r1, #GAFR0_L_OFFSET]

        ldr     r2, =0x59E540D2
        str     r2, [r1, #GAFR0_U_OFFSET]
	
        ldr     r2, =0x9892004A
        str     r2, [r1, #GAFR1_L_OFFSET]
	
        
	  
        ;set gpio78 to nCS<2> wangshu 2004-11-30
        ldr     r2, =0x6AAAAAAA
        str     r2, [r1, #GAFR2_L_OFFSET]
	
	ldr     r2, =0xAAA580AA
        str     r2, [r1, #GAFR1_U_OFFSET]
	
        ldr     r2, =0x55A9A3FA
        str     r2, [r1, #GAFR2_U_OFFSET]

        ;Clear GPIO98 wangshu 2004-11-30
        ldr     r2, =0x5452550C         
        str     r2, [r1, #GAFR3_L_OFFSET]

        ldr     r2, =0x00001445
        str     r2, [r1, #GAFR3_U_OFFSET]

        
        ldr     r0, =PWR_BASE_PHYSICAL
        mov     r1, #0x30                             ; set-to-clear RDH and PH
        str     r1, [r0, #PSSR_OFFSET]

         
        ldr     r2,  =PWR_BASE_PHYSICAL

        ; init the PCFR
        ; *NOTE:.
        ;
        ldr	r1, [r2, #PCFR_OFFSET]
        bic     r1, r1,#0x10    
        str     r1, [r2, #PCFR_OFFSET]
        
        mov  pc, lr



;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITMEMC
        ; ********************************************************************            
        ; Initlialize Memory Controller
        ;   The sequence below is based on the recommended init steps detailed
        ;     in the EAS, chapter 13.
        ;

        ; pause for 200 uSecs- allow internal clocks to settle
        ; *Note: only need this if hard reset... doing it anyway for now
        ;


      ;---- Wait 200 usec
        ldr r3, =OST_BASE_PHYSICAL                   ; reset the OS Timer Count to zero
        ldr r2, [r3, #OSCR0_OFFSET] 
        ldr r4, =0x300          ; really 0x2E1 is about 200usec, so 0x300 should be plenty
10
        ldr r0, [r3, #OSCR0_OFFSET] 
        sub r0, r0, r2
        cmp r4, r0
        bgt %B10


        ; Query the ROM devices: issue "Read Device Identifier" Command
        ;   L18: 0x880C
	;   K18: 0x8806
        ;   J3:  0x18
        ;
        
        ; First, enable ICache so that I can take the Flash out of read-array mode safely (MMU of defaults to ICacheable, need MMU on for DCacheability).
        ;   Then, lock the section of code that manipulates the flash into i$.
        ;
        ; *16-bit FLASH consideration:  I expect the following 32-bit pokes to generate 2 16-bit cycles if 16-bit flash.  Would be bad.
        ;    So, options:
        ;       1) just do single device acesses:  so, upper 16 of data on 32-bit writes = 0 ... what does this do on a write if parallel devices?
        ;       2) handle differently for 16 -vs- 32-bit flash devices?  How will MEMC break up?
        ;
        
        add     r3, pc, #LOCKME-(.+8)
        mvn     r0, #31
        and     r1, r3, r0                  ; ensure is 32-byte aligned

        add     r2, pc, #LOCKMEEND-(.+8)
        and     r2, r2, r0                  ; ensure is 32-byte aligned
        
        mrc     p15, 0, r0, c1, c0, 0       ; read (0x78) cp15.1
        orr     r0, r0, #0x1000             ; enable ICache
        mcr     p15, 0, r0, c1, c0, 0       ; write it
        CPWAIT  r0
        
        mcr     p15, 0, r0, c9, c1, 1       ; unlock entire i$
        mcr     p15, 0, r0 ,c7, c5, 0       ; flush i$ and BTB
        
LOCKLOOP
        mcr     p15, 0, r1, c7, c5, 1       ; CYA: invalidate i$ line (same as we are about to lock - CAN affect a locked line!)
        mcr     p15, 0, r1, c9, c1, 0       ; lock line into icache, based on r1
        cmp     r1, r2                      ; are we done?
        add     r1, r1, #32                 ; increment to next cache-line
        bne     LOCKLOOP                                                                    


   ALIGN 32                                 ; ensure is cache-line aligned (i.e. 32 Bytes = 2^5)
LOCKME
        ; First, Read Device Identifier to obtain RCR value (a 2 cycle operation)
        ;
        mov     r0, #0x0  
        ;ldr     r2, =0x00980098            ; write "Read Query" (*NOTE: Consideration for cases where only a single FLASH: memc might break up into 2 commands for single flash!)
        mov     r2, #0x0098
        mov     r2, r2 LSL #16
        orr     r2, r2, #0x0098
        str     r2, [r0]
        
        mov     r0, #0x4                 ; Read 2nd word: "Device Code" entry in Query Structure        
        ldr     r8, [r0]                    ; 2nd cycle; r8 now contains the device code on upper and lower halves of data bus.

        mov     r0, #0x0  
        ;ldr     r1, =0x00FF00FF     
        mov     r1, #0x00FF
        mov     r1, r1 LSL #16
        orr     r1, r1, #0x00FF
        str     r1, [r0]                    ; put back into read array mode
   
   ALIGN 32
LOCKMEEND    nop


        mcr     p15, 0, r0, c9, c1, 1       ; unlock entire i$
        mov     r0, #0x78
        mcr     p15, 0, r0, c1, c0, 0       ; disable i$ now that we are done with it
        CPWAIT r0
        mcr     p15, 0, r0 ,c7, c5, 0       ; flush i$ and BTB
  

        ; get memory controller base address
        ldr     r1,  =MEMC_BASE_PHYSICAL

; ****************************************************************************
;   Step 1
;
        ;
        ; Initialize Static Memory Timings
        ;

        ; write msc0, read back to ensure data latches
        ;
	
        ldr     r2,   =MSC0_VAL
        str     r2,   [r1, #MSC0_OFFSET]
        ldr     r2,   [r1, #MSC0_OFFSET]

        ; write msc1

        ldr     r2,  =MSC1_VAL
        str     r2,  [r1, #MSC1_OFFSET]
        ldr     r2,  [r1, #MSC1_OFFSET]
    
        ; write msc2
        ldr     r2,  =MSC2_VAL
        str     r2,  [r1, #MSC2_OFFSET]
        ldr     r2,  [r1, #MSC2_OFFSET]
	
        ;
        ; Initialize Card Timings
        ;
	;bl ledflash 
        ; write mecr
        ldr     r2,  =0x0
        ;ldr     r2,  =0x0
        ;chang by zzc,if have 2 PC card MECR=1 elsif MECR=0
        str     r2,  [r1, #MECR_OFFSET]
  	
        ; write mcmem0
        ldr     r2,  =MCMEM0_VAL
        str     r2,  [r1, #MCMEM0_OFFSET]
	
        ; write mcatt0
        ldr     r2,  =MCATT0_VAL
        str     r2,  [r1, #MCATT0_OFFSET]

        ; write mcio0
        ldr     r2,  =MCIO0_VAL
        str     r2,  [r1, #MCIO0_OFFSET]
	
        
        ;
        ; Initialize Fly-By-DMA
        ;
        
        ; write flycnfg
        ldr     r2,  =FLYCNFG_VAL
        str     r2,  [r1, #FLYCNFG_OFFSET]

        ;-------------------------------------------------------
        ; 4th bullet, Step 1 : if coming out of Sleep, must explicitly 
        ;   CLEAR all SDRAM partitions via MDCNFG[17:16, 1:0]. *
        ;
;        IF :DEF: TESTSLEEP
            ; need to check RCSR status here... inserting config code, will need cmp later
            tst       r10, #(xlli_RCSR_SMR)
            beq     memNotSleepReset
            ldr     r2,  [r1, #MDCNFG_OFFSET]
            bic     r2,  r2,  #(MDCNFG_DE0 :OR: MDCNFG_DE1)
            bic     r2,  r2,  #(MDCNFG_DE2 :OR: MDCNFG_DE3)
            str     r2,  [r1, #MDCNFG_OFFSET]
;        ENDIF    
memNotSleepReset           
 
 	
        ;-------------------------------------------------------
        ; 5th Bullet, Step 1
        ;
        
        ; get the mdrefr settings
        ;
        ldr     r3,  =MDREFR_VAL
        
        ; extract DRI field (we need a valid DRI field)
        ;
        ldr     r2,  =0xFFF
        
        ; valid DRI field in r3
        ;
        and     r3,  r3,  r2                 
        
        ; get the reset state of MDREFR
        ;
        ldr     r4,  [r1, #MDREFR_OFFSET]
        
        ; clear the DRI field
        ;
        bic     r4,  r4,  r2
        
        ; insert the valid DRI field loaded above
        ;
        orr     r4,  r4,  r3
 
        ; enable K0Run*
        ;
        orr     r4, r4, #MDREFR_K0RUN
        orr     r4, r4, #MDREFR_K2RUN
        
        ; configure kxdb2*
        ;
        ;bic     r4, r4, #MDREFR_K0DB2
        ;bic     r4, r4, #MDREFR_K1DB2
        ;bic     r4, r4, #MDREFR_K2DB2

        orr     r4, r4, #MDREFR_K0DB2
        orr     r4, r4, #MDREFR_K1DB2
        orr     r4, r4, #MDREFR_K2DB2

        ;  Set MDREFR.K0DB4 for SDCLK[0] = MemClk/4*
        ;
        orr    r4, r4, #MDREFR_K0DB4 
        ;bic     r4, r4, #MDREFR_K0DB4

        ; clear the free-running clock bits, if required.
        ;  (clear K1Free, K2Free)*
        ;
        bic     r4,  r4,  #(MDREFR_K0FREE :OR: MDREFR_K1FREE :OR: MDREFR_K2FREE)
        
        ; Set K0Free (as per Mainstone spec...) *
        ;
        ;orr     r4,  r4,  #MDREFR_K0FREE
        
        ; write back mdrefr
        ;
        str     r4,  [r1, #MDREFR_OFFSET]

        ; *Note: preserve the mdrefr value in r4 *

 
; ****************************************************************************
;   Step 2: Not configuring SXCFNG here; doing it after INITCLKS
;


; ****************************************************************************
;   Step 3
;

        ; Assumes previous mdrefr value in r4, if not then read current mdrefr.
        ; Assumes boot FLASH ID still in R8.

        ; 1st Bullet: set K1RUN if bank 0 installed
        ;
        orr   r4,  r4,  #MDREFR_K1RUN



        ;orreq    r4, r4,  #0x00020000     ; SDClk[1] = MemClk/2
        ;bicne    r4, r4,  #0x00020000     ; SDClk[1] = MemClk

   ALIGN
SYNCDONE
        ;
        ; Need to force sdclk to be halved and alter MSCs for some freqs
        ;

        ;ldr    r2, [r1, #MSC0_OFFSET]       ; get current MSC0 value... will be adjusting it

        ;
        ;       ~~ ADJUST MSC0 for Higher MemClks ~~
        ;
        ; **NOTE: It is invalid to run J3 on mainboard at MemClk = 130MHz **
        ;   Therfore, targetting MemClk = 117 MHz, which is possible to acheive.
        
        ;bicge    r2, r2, #0x7F00            ; clear RRR0 and RDN0 for J3
        ;orrge    r2, r2, #0x5A00            ; set RRR0 = 5, and RDN0 = 10 (0xA) for J3
        ;bicge    r2, r2, #0xF00000          ; clear current RDF1 for K3/18
        ;orrge    r2, r2, #0xE00000          ; set RDF1 = 14 (0xE) for K3/18
        
        
        ;str    r2, [r1, #MSC0_OFFSET]       ; store it back
        ;ldr    r2, [r1, #MSC0_OFFSET]       ; ensure it latches

        ;
        ; Enforce/override halving where needed, regardless of CPU stepping
        ;  (the user needs to be careful with A0's VCC_MEM:  see release notes and EMT)
        ;
        ;orr      r4, r4,  #0x00020000         ; SDClk[1] = MemClk/2 regardless of what user wants  
        
        ;                                                                                       ;
        ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

   ALIGN
NOADJUSTMENT
        ; write back mdrefr
        ;
        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]


        ; 2nd Bullet: deassert SLFRSH
        ;